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US 7,127,002 B1Granted
System and method for frequency and phase modulating data on a SCSI bus or a serial SCSI link
AssigneeAdaptec, Inc.
InventorFadi A. Mahmoud
Life of this patent
Estimating the term…
Abstract
A system and a method for multiplying data throughput in a SCSI bus includes identifying multiple frequencies within a bandwidth of a SCSI bus. A binary value is assigned to each one of the multiple frequencies. One of the multiple frequencies is selected. The assigned binary value of the selected frequency corresponds to a set of bits to be transmitted during a first sampling cycle. The selected frequency is transmitted on the SCSI bus during the first sampling cycle.
Claims13
A system for multiplying data throughput in a SCSI bus comprising:
- a transmitter including:
- an data input;
- a modulator;
- a first phase locked loop (PLL) circuit, the first PLL for stabilizing a clock signal, the stabilized clock signal being coupled to the modulator;
- logic for identifying a plurality of phases within a bandwidth of a SCSI bus;
- logic for assigning a binary value to each one of the plurality of phases;
- logic for selecting one of the plurality of phases wherein the assigned binary value of the selected phase corresponding to a plurality of bits to be transmitted during a first sampling cycle;
- and
- logic for transmitting the selected phase on the SCSI bus during the first sampling cycle;
- a receiver, the receiver being coupled to the transmitter by a SCSI bus, the receiver including:
- a demodulator;
- an adding circuit having a first input coupled to an output of the demodulator;
- a second PLL circuit having an input coupled to the stabilized clock signal from the first PLL circuit and having an output coupled to a second input to the adding circuit;
- logic for receiving the selected phase in a receiver during the first sampling cycle;
- logic for identifying the selected phase;
- logic for determining the corresponding assigned binary value of the selected phase;
- and
- logic for outputting the corresponding assigned binary value of the selected phase.
15 more elements
A system for multiplying data throughput in a SCSI bus comprising:
- a transmitter including:
- a data input;
- and
- a first phase locked loop (PLL) circuit for shifting the phase of a base reference signal according to an input signal applied to the data input;
- a second PLL circuit for stabilizing a clock signal;
- logic for identifying a plurality of phases within a bandwidth of a SCSI bus;
- logic for assigning a binary value to each one of the plurality of phases;
- logic for selecting one of the plurality of phases wherein the assigned binary value of the selected phase corresponding to a plurality of bits to be transmitted during a first sampling cycle;
- and
- logic for transmitting the selected phase on the SCSI bus during the first sampling cycle;
- a receiver, the receiver being coupled to the transmitter by a SCSI bus, the receiver including:
- a third PLL circuit, the third PLL circuit for comparing a base reference signal to the phase shifted data signal output from the transmitter, the third PLL circuit having an output;
- an adding circuit having a first input coupled to an output of the third PLL circuit;
- a fourth PLL circuit having an input coupled to the stabilized clock signal from the second PLL circuit and having an output coupled to a second input to the adding circuit;
- logic for receiving the selected phase in a receiver during the first sampling cycle;
- logic for identifying the selected phase;
- logic for determining the corresponding assigned binary value of the selected phase;
- and
- logic for outputting the corresponding assigned binary value of the selected phase.
16 more elements
Dependencies are inferred from the claim text.