Method and system for transmission and reception of asynchronously multiplexed signals

A communication method comprising the steps of:

• a) producing, for a first payload signal of a first data unit, first header bits equal in number to second header bits of a second payload signal of a second data unit;
• b) dividing said first header bits by a generator polynomial to produce a first error check code, said generator polynomial being equal to a generator polynomial with which said second header bits are divided to produce a second error check code;
• c) producing a sum of a remainder of division of hypothetical header bits by said generator polynomial to said first error check code, said hypothetical header bits being greater in number than said first header bits;
• d) forming said first data unit with said first header bits, said sum and said first payload signal;
• and
• e) distinguishing between a received first data unit and a received second data unit based on different error check results between the received first data unit and the received second data unit.

A communication circuit comprising:

• a storage circuit including a first field for storing first header bits of a first payload signal of a first data unit, a second field containing a first error check code resulting from division of said first header bits by a generator polynomial, and a third field for storing said first payload signal, said first header bits being equal in number to second header bits of a second payload signal of a second data unit, and said generator polynomial being used to divide the second header bits to produce a second error check code;
• division circuitry for dividing the first header bits by said generator polynomial to produce said first error check code;
• and
• adder circuitry for summing a remainder of division of hypothetical header bits by said generator polynomial to said first error check code to produce a sum and inserting the sum into said second field of the storage circuit, the hypothetical header bits being greater in number than a total number of bits in said first and second fields, whereby the first and second data units can be distinguished from each other by different error check results of the first and second data units.