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US 7,126,870 B2Granted
Integrated semiconductor memory with sense amplifier
AssigneeInfineon Technologies AG
InventorsHelmut Schneider, Michael Bernhard Sommer
Life of this patent
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Abstract
An integrated semiconductor memory includes a sense amplifier with a first subamplifier for driving memory cells of a first memory cell array and a second subamplifier for driving memory cells of a second memory cell array. The subamplifiers are connected via continuous lines to bit lines of the first memory cell array and to bit lines of the second memory cell array. The subamplifiers can be operated by applying a single control signal (MUXl, MUXr) in a first operating state for reading in, reading out, and refreshing information of the memory cells and in a second operating state for precharging the bit lines. Reduction of the signal line due to losses is avoided as a result of direct coupling the subamplifiers to the respective memory cell arrays.
Claims16
An integrated semiconductor memory with sense amplifier, comprising:
- a memory cell array with a first bit line (BLl′) and a second bit line (/BLl′);
- and
- the sense amplifier (100a) including a first signal line (BSAl), a second signal line (/BSAl), and a first control terminal (MINl) for applying a first control signal (MUXl),
- wherein the first and second bit lines (BLl′, /BLl′) of the memory cell array and the first and second signal lines (BSAl, /BSAl) of the sense amplifier (100a) are formed as continuous interconnectors (BLl′, /BLl′, BSAl, /BSAl),
- the first bit line (BLl′) of the memory cell array being connected to the first signal line (BSAl) of the sense amplifier (100a) via a first continuous interconnect (BLl′, BSAl) and the second bit line (/BLl′) of the memory cell array being connected to the second signal line (/BSAl) of the sense amplifier via a second continuous interconnect (/BLl′, /BSAl),
- the sense amplifier (100a) including a first circuit unit (10a) having a first switching transistor (11a) with a first control terminal (S11a), having a second switching transistor (12a) with a second control terminal (S12a), and having a third switching transistor (13a) with a third control terminal (S13a), the respective control terminals (S11a, S12a, S13a) of the switching transistors (11a, 12a, 13a) of the first circuit unit (10a) being connected to the first control terminal (MINl) for applying the first control signal (MUXl), the first circuit unit (10a) being designed to connect the first signal line (BSAl) of the sense amplifier to the second signal line (/BSAl) of the sense amplifier at a high impedance or at a low impedance depending upon a state of the first control signal (MUXl),
- the sense amplifier (100a) including a first and a second switching transistor (THa, TLa), each having a control terminal (S1a, S2a), each control terminal being driven by the first control signal (MUXl), the sense amplifier (100a) including a second circuit unit (20a) for feeding a first voltage potential (VBLH) to the first or second signal line (BSAl, /BSAl) of the sense amplifier, the first voltage potential (VBLH) being fed to the second circuit unit (20a) via the first switching transistor (THa) of the sense amplifier, the second circuit unit (20a) being designed to feed the first voltage potential (VBLH) to the first or second signal line of the sense amplifier if the first switching transistor (THa) of the sense amplifier is turned on by the first control signal (MUXl),
- the sense amplifier (100a) includes a third circuit unit (30a) for feeding a second voltage potential (VBLL) to the first or second signal line (BSAl, /BSAl) of the sense amplifier, the second voltage potential (VBLL) being fed to the third circuit unit (30a) via the second switching transistor (TLa) of the sense amplifier, the third circuit unit (30a) being designed to feed the second potential voltage (VBLL) to the first or second signal line of the sense amplifier, if the second switching transistor (TLa) of the sense amplifier is turned on by the first control signal (MUXl),
- the first and second switching transistors of the sense amplifier are designed as a switching transistor of the n-channel type (THa, TLa), and
- the switching transistors of the first circuit unit (10a) are designed as thick-oxide switching transistors of the p-channel type (11a, 12a, 13a).
7 more elements
A method for operating an integrated semiconductor memory with a sense amplifier, comprising:
- applying a first state of a first control signal (MUXl) to a first control terminal (MINl) of the sense amplifier (10a);
- controlling first, second, and third switching transistors (11a, 12a, 13a) of the first circuit unit (10a) into an off state;
- controlling first, second, and third switching transistors (THa, TLa, TSa) of the sense amplifier (100a) into an on state;
- applying a first state of a second control signal (CSL) to a second control terminal (CIN) of the sense amplifier;
- controlling first and second switching transistors (41a, 42a) of a fourth circuit unit (40a) into the on state, whereby a first signal line (BSAl) of the sense amplifier is connected to a first data line (LDQ) and a second signal line (/BSAl) of the sense amplifier is connected to a second data line (/LDQ) at a low impedance;
- and
- carrying out a read or write access in the memory cell array.
4 more elements
Dependencies are inferred from the claim text.