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US 7,126,866 B1Granted
Low power ROM architecture
AssigneeNational Semiconductor Corporation
InventorsPavel Poplevine, Ernes Ho, Hengyang Lin, Andrew J. Franklin
Life of this patent
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Abstract
In a ROM structure, power consumption is reduced by providing for pre-discharging of only the bit line corresponding to the memory location that is being read. Column select lines are coupled to logic to switch in a pre-discharging circuit prior to reading, and to disconnect, from the pre-discharging circuit during reading, only the bit line corresponding to the memory location being read.
Claims18
A method for providing a low power ROM structure, comprising
- performing a pre-discharging step prior to a read operation, wherein the pre-discharging step includes selective connection and disconnection of individual selected bit lines, selected from the total number of bit lines, to and from a pre-discharging circuit, and
- connecting the bit line to a sense amplifier after the pre-discharging, to facilitate reading without the need for pre-charging any of the bit lines.
A ROM structure, comprising
- a memory core with a matrix of bit lines and word lines,
- a plurality of memory cells at predetermined intersections of the bit lines and word lines,
- a pre-discharging circuit,
- a read circuit, and
- logic to select individual specific bit lines from the total number of bit lines, for pre-discharging and for thereafter connecting the read circuit to read one or more specific bit lines, the read circuit providing current to said one or more specific bit lines thereby avoiding the need for pre-charging any of the bit lines prior to reading.
2 more elements
Dependencies are inferred from the claim text.