Memory device including parallel test circuit

Abstract

A memory device including a parallel test circuit can overcome a channel deficiency phenomenon of test equipment by reducing the number of input/output pads. The memory device including a parallel test circuit comprises a burst length regulating block, a parallel test block, an output block and a plurality of input/output pads. The burst length regulating block sets a second burst length at a test mode which is longer than a first burst length at a normal mode. The parallel test block compresses data and tests the compressed data by a repair unit. The output block sequentially outputs data outputted from at least two or more parallel test blocks depending on the second burst length. The plurality of input/output pads externally output data outputted from the output block.

Dependencies are inferred from the claim text.