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US 7,126,864 B2Granted
Memory device capable of changing data output mode
AssigneeHynix Semiconductor Inc.
InventorJun Seop Chung
Life of this patent
Estimating the term…
Abstract
Disclosed herein is a memory device capable of changing data output modes. According to the present invention, an address that is input to a circuit, which is designed in 8-bit output mode, is internally modified, to operate in 16-bit output mode, and a test operation is performed in 8-bit output mode. As such, two kinds of output mode circuits can be tested in one test equipment. Accordingly, test efficiency can be enhanced and costs can be saved.
Claims25
A memory device, comprising:
- an address comparator in which a fail address used to select a fail cell is stored on an 8-bit output mode basis, wherein the address comparator compares an address signal and the fail address, and generates a repair enable signal if the address signal and the fail address coincide with each other;
- an address signal controller which transfers the address signal in entirety to the address comparator in the 8-bit output mode, and transfers address bits of the address signal that are used only in the 8-bit output mode as a given logic value, so that the transferred address bits are not compared in a 16-bit output mode according to an output mode decision signal and a 8-bit forced decision signal;
- and
- a fail bit signal generator that generates fail bit signals that indicate to which bit of output data does fail data of the fail cell correspond according to the repair enable signal,
- wherein although information on the fail address is stored on the 8-bit output mode basis, the memory device is configured to operate as the 8-bit output mode or the 16-bit output mode according to the output mode decision signal and the 8-bit forced decision signal.
2 more elements
A memory device, comprising:
- a cell array including a plurality of cells, configured to output data according to an address signal;
- a redundancy array including a plurality of repair cells, configured to output repair data that will replace fail data output from a fail cell of the cell array according to the address signal;
- a fail bit detector in which a fail address used to select the fail cell is stored according to a first output mode, wherein the fail bit detector compares the address signal and the fail address in the first output mode according to an output mode decision signal and an m-bit forced decision signal, and compares an address bit located within an address signal used to signify a second output mode with the fail address, thus outputting a fail bit signal which indicates which bits are in error;
- and
- an I/O multiplexer configured to output the repair data instead of the fail data according to the fail bit signal, and output m bits of data in the first output mode, and output n bits of data in the second output mode,
- wherein information on the fail address is stored according to the first output mode, and the memory device is configured to operate in the first output mode or the second output mode according to the output mode decision signal and the m-bit forced decision signal.
3 more elements
Dependencies are inferred from the claim text.