Read-accessible column latch for non-volatile memories
AssigneeAtmel Corporation
InventorsJerome Pratlong, Marc Merandat, Stephane Ricard, Sylvie B. Vergnes, Laureline Bour
Life of this patent
Estimating the term…
Abstract
Program column latch circuitry of nonvolatile memory is provided with read-back capability to verify that data bits have been correctly loaded into the latch circuits and written to the memory cells. The interface between the low voltage latches and the external input and output data paths is provided with opposite-facing tri-state buffers that allow latched data to be read out for comparison and verification. Writing of latched data to memory cells can be verified by the read-back without needing any external RAM.
Claims15
A read-accessible column latch circuit, comprising:
- a low voltage latching portion and a high voltage data writing portion coupled together through a first transmission gate, the first transmission gate configured to be responsive to a data transfer signal in a write mode;
- a first interface means coupling external input and output data paths to the low voltage latching portion, the first interface means configured to be responsive to load and read-back mode signals for selecting a data flow direction between the data paths and the low voltage latching portion and enabling data transfer through the interface means;
- and
- a second interface means for coupling the high voltage data writing portion to a bit line for a column of memory cells.
A read-accessible column latch circuit for non-volatile memories, comprising:
- a pair of opposite-facing tri-state buffers coupled to external input and output data paths leading respectively to and from the column latch circuit and configured to select a data flow direction, the tri-state buffers never both active simultaneously;
- a latching circuit coupled to the tri-state buffers, the latching circuit configured to receive, from the external input data path, data to-be-loaded through one of the tri-state buffers in a load mode of a programming operation, and to read back latched data through the other of the tri-state buffers to the external output data path in a read-back mode of the programming operation;
- a first transmission gate coupled to the latching circuit the first transmission gate configured to allow transmission through the gate of latched data at the start of a write mode of the programming operation;
- a level-shifting circuit coupled to the transmission gate, the level-shifting circuit configured to shift a voltage corresponding to the data to a voltage needed for programming memory cells of the non-volatile memories in accord with the data;
- and
- a second transmission gate configured to couple the level-shifting circuit to a bit line leading to a column of non-volatile memory bit cells, such that data are written to selected bit cells in a write mode.
A method of operating program column latch circuitry for programming a non-volatile memory, comprising:
- (a) loading addressed latching circuits of the program column latch circuitry with data bits from an external input data path;
- (b) writing the latched data bits to addressed memory cells of a non-volatile memory;
- (c) reading back latched data bits from the latching circuits to an external output data path and verifying whether the data bits in the addressed memory cells have been correctly written;
- and
- (d) if the verifying indicates incorrect writing, then repeating steps (b) and (c) until data bits have been verified as correctly written.
Dependencies are inferred from the claim text.