US 7,126,858 B1 · Apparatus for emulating asynchronous clear in memory structure and method for implementing the same

Abstract

Circuitry is disclosed for emulating asynchronous clear on each of a read address register of a memory cell and a data output register of a memory cell such that the memory cell can be defined in a memory structure that does not support asynchronous clear capability. The emulation includes defining the memory cell to have a registered read address input and a data output connected to an input of a multiplexer. The register connected to the read address input of the multiplexer does not include an asynchronous clear connection. The data transmitted from the memory cell to the multiplexer is output from the multiplexer when an asynchronous clear signal has not been asserted. However, the multiplexer is further connected to output either null data or a ground signal in lieu of the data transmitted from the memory cell when an asynchronous clear signal has been asserted.

Claims20

Dependent claims

A method for emulating asynchronous clear on a read address register of a memory cell, comprising:

connecting a first register to a read address input of a first memory cell, wherein the first register does not include an asynchronous clear connection;
connecting a data output of the first memory cell to a first input of a multiplexer;
connecting a read address input of a second memory cell to a ground signal;
connecting a data output of the second memory cell to a second input of the multiplexer;
generating a select signal to have a state opposite that of an asynchronous clear signal;
and
using the select signal to control the multiplexer, wherein a non-asserted state of the select signal causes the multiplexer to output data received at the second input of the multiplexer from the data output of the second memory cell, wherein an asserted state of the select signal causes the multiplexer to output data received at the first input of the multiplexer from the data output of the first memory cell.

4 more elements

A method for emulating asynchronous clear on a data output register of a memory cell, comprising:

connecting a register to a read address input of a memory cell, wherein the register does not include an asynchronous clear connection;
connecting a data output of the memory cell to a first input of a multiplexer;
connecting a ground signal to a second input of the multiplexer;
generating a select signal to have a state opposite that of an asynchronous clear signal;
and
using the select signal to control the multiplexer, wherein a non-asserted state of the select signal causes the multiplexer to output the ground signal received at the second input of the multiplexer, wherein an asserted state of the select signal causes the multiplexer to output data received at the first input of the multiplexer from the data output of the memory cell.

3 more elements

A circuit for emulating asynchronous clear on a read address register of a memory cell, comprising:

a first memory cell having a read address input and a data output;
a first register having a data output connected to the read address input of the first memory cell, wherein the first register is not connected to receive an asynchronous clear signal;
a second memory cell having a read address input and a data output, wherein the read address input is connected to receive a ground signal;
and
a multiplexer having a first data input connected to receive data from the data output of the first memory cell, the multiplexer having a second data input connected to receive data from the data output of the second memory cell, the multiplexer having a select signal input connected to receive a select signal having a state opposite that of an asynchronous clear signal, the multiplexer being configured to transmit data received at the first data input of the multiplexer to a data output of the multiplexer when the select signal has an asserted state, the multiplexer being configured to transmit data received at the second data input of the multiplexer to the data output of the multiplexer when the select signal has a non-asserted state.

2 more elements

A circuit for emulating asynchronous clear on a data output register of a memory cell, comprising:

a memory cell having a read address input and a data output;
a register having a data output connected to the read address input of the memory cell, wherein the register is not connected to receive an asynchronous clear signal;
and
a multiplexer having a first data input connected to receive data from the data output of the memory cell, the multiplexer having a second data input connected to receive a ground signal, the multiplexer having a select signal input connected to receive a select signal having a state opposite that of an asynchronous clear signal, the multiplexer being configured to transmit data received at the first data input of the multiplexer to a data output of the multiplexer when the select signal has an asserted state, the multiplexer being configured to transmit data received at the second data input of the multiplexer to the data output of the multiplexer when the select signal has a non-asserted state.

1 more element

Dependencies are inferred from the claim text.

Apparatus for emulating asynchronous clear in memory structure and method for implementing the same

Life of this patent

Apparatus for emulating asynchronous clear in memory structure and method for implementing the same

Life of this patent

Abstract

Claims20