Storage subsystem with embedded circuit for protecting against anomalies in power signal from host
AssigneeSiliconSystems, Inc.
InventorMichael J. Hajeck
Life of this patent
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Abstract
A storage subsystem, such as a flash memory card, includes a voltage detection circuit that monitors the power signal from a host system to detect anomalies. The voltage detection circuit responds to a power signal anomaly by asserting a signal, such as a busy signal on a standard ready/busy signal line, to block the host system from performing write operations to the storage subsystem during presence of the anomaly. The storage system may also include a backup power source, such as a charge pump circuit, a capacitive array, and/or a rechargeable battery, that provides power to a controller of the storage subsystem during the presence of the anomaly, such that the storage system can complete outstanding operations.
Claims32
A memory subsystem that protects against data losses caused by power signal anomalies, the memory subsystem comprising:
- a solid state non-volatile memory array;
- a controller that transfers data between a host system and the solid state non-volatile memory array;
- a regulation circuit that receives a power signal from the host system, and generates a regulated power signal that is provided to the controller;
- and
- a voltage detection circuit that monitors the power signal from the host system to detect anomalies therein, wherein the voltage detection circuit responds to detection of an anomaly in the power signal by causing a busy signal to be asserted to the host system, to thereby block the host system from performing write operations to the memory subsystem during presence of the anomaly;
- wherein the memory subsystem is configured for pluggable attachment to the host system.
A method of responding to anomalies in a power signal provided by a host system to a storage subsystem, the method comprising, with the storage subsystem:
- receiving the power signal from the host system, said host system being separate from the storage subsystem and pluggably connecting to the storage subsystem;
- detecting an anomaly in the power signal with a detection circuit of the storage subsystem;
- and
- in response to detection of the anomaly by the detection circuit, asserting a signal to the host system to inhibit the host system from writing data to the storage subsystem during presence of the anomaly.
A solid state memory subsystem, comprising:
- a solid state, non-volatile memory array;
- a controller that writes data to, and reads data from, the non-volatile memory array in response to operations initiated by a host system;
- a regulation circuit that receives a power signal from the host system and generates a regulated power signal that is provided to the controller;
- a voltage detection circuit that monitors the power signal from the host system to detect anomalies therein;
- and
- a signal generation circuit that generates a busy signal to the host system when either or both of the following occur:
- (a) an anomaly is detected by the voltage detection circuit, (b) the controller is in a busy state.
Dependencies are inferred from the claim text.