Semiconductor device that enables simultaneous read and write/read operation

A nonvolatile semiconductor memory device which comprises at least two cores, each of which includes a set of electrically rewritable nonvolatile memory cells, and which is capable of reading data in one core while rewriting/erasing data in the other core, comprising:

• a common reference transistor passing through a common reference current;
• a first and a second current source transistors driven in parallel by a potential determined by the common reference current, the first current source transistor passing through a first reference current used in a data reading and the second current source transistor passing through a second reference current used in a data rewriting/erasing;
• a first comparator comparing a current from the one core with the first reference current;
• and
• a second comparator comparing a current from the other core with the second reference current.

A nonvolatile semiconductor memory device simultaneously carrying out a read operation and a write/erase operation, comprising:

• a common reference transistor supplying a common reference current;
• a first and a second current source transistors driven in parallel by a potential determined by the common reference current, the first current source transistor supplying a first reference current for the read operation and the second current source transistor supplying a second reference current for the write/erase operation;
• a first comparator comparing the first reference current with a current of data read out by the read operation;
• and
• a second comparator comparing the second reference current with a current of data read out by the write/erase operation.

A nonvolatile semiconductor memory device comprising;

• a first reference signal provided through a dummy gate;
• a first data signal provided through a gate;
• a first data comparator circuit that compares said first reference signal and said first data signal during a read operation;
• a second reference signal provided through a second dummy gate;
• a second data signal provided through a second gate;
• and
• a second data comparator circuit that compares said second reference signal and said second data signal during a verify read operation.