Technique for programming floating-gate transistor used in circuitry as flash EPROM

A method of programming a group of memory elements respectively comprising like-polarity floating-gate field-effect transistors (“FETs”) of an erasable programmable read-only memory in which each FET has (a) first and second source/drain regions laterally separated from each other by a channel portion of a body region that forms a pn junction with each source/drain region, (b) a floating-gate electrode laterally adjacent to the first source/drain region and overlying a first part of the channel portion, and (c) a select-gate electrode laterally adjacent to the second source/drain region, spaced apart from the floating-gate electrode, and overlying a second part of the channel portion lateral to the first portion of the channel portion, each FET being in an erased condition with a programmable threshold voltage is (a) less than a first transition value VT1 if that FET is of n-channel type and (b) greater than −VT1 if that FET is of p-channel type, each FET being in a programmed condition when its programmable threshold voltage is (a) greater than a second transition value VT2 if that FET is of n-channel type and (b) less than −VT2 if that FET is of p-channel type where VT2 exceeds or equals VT1, the method comprising:

• selecting a group of the FETs that are initially in their erased conditions and are to be selectively placed in their programmed conditions;
• changing first voltages applied respectively to the first source/drain regions of the selected FETs from respective nominal first values to respective programming first values;
• controlling second voltages applied respectively to the second source/drain regions of the selected FETs so that the second voltage for each selected FET (a) changes from a nominal second value to a programming-inhibit value if that FET is to remain in its erased condition and (b) stays largely at the nominal second value if that FET is to be placed in the programmed condition;
• and
• changing select voltages respectively applied to the select-gate electrodes of the selected FETs from respective nominal select values to respective programming-enable select values such that each selected FET (a) remains in its erased condition if its second voltage goes to the programming-inhibit value for that scrod voltage and (b) enters its programming condition if its second voltage stays largely at the nominal value for that second voltage and such that, in each instance where one of the selected FETs is to remain in its erased condition, the select voltage for that selected FET starts to change from the nominal value for that select voltage to its programming-enable value after the second voltage for that selected FET starts to change from the nominal value for that second voltage to its programming-inhibit value.

An electronic circuit comprising:

• a floating-gate field-effect transistor (“FET”) which comprises (a) first and second source/drain regions laterally separated from each other by a channel portion of a body region that forms a pn junction with each source/drain region, (b) a floating-gate electrode laterally adjacent to the first source/drain region and overlying a first part of the channel portion, and (c) a select-gate electrode laterally adjacent to the second source/drain region, spaced apart from the floating-gate electrode, and overlying a second part of the channel portion lateral to the first part of the channel portion, the FET being in an erased condition with a programmable threshold voltage (a) less than a first transition value VT1 if the FET is of n-channel type and (b) greater than −VT1 if the FET is of p-channel type, the FET being in a programmed condition when its programmable threshold voltage is (a) greater than a second transition value VT2 if the FET is of n-channel type and (b) less than −VT2 if the FET is of p-channel type where VT2 exceeds or equals VT1;
• first control circuitry which applies a first voltage to the first source/drain region and is operable to change the first voltage from a nominal first value to a programming first value during a programming operation;
• second control circuitry which applies a second voltage to the second source/drain region and is operable (a) to change the second voltage from a nominal second value to a programming-inhibit second value during a programming operation if the FET is initially in the erased condition and is to remain in the erased condition and (b) to maintain the second voltage largely at the nominal second value during the programming operation if the FET is to be placed in its programmed condition;
• and
• select-gate control circuitry which applies a select voltage to the select-gate electrode and is operable to change the select voltage from a nominal select value to a programming-enable select value during a programming operation such that, when the FET was in the erased condition prior to a programming operation, the FET (a) remains in the erased condition during that programming operation if the second voltage goes to its programming-inhibit value during that programming operation and (b) enters the programmed condition during that programming operation if the second voltage stays largely at its nominal value during that programming operation and such that, in an instance where the FET is to remain in the erased condition during a programming operation, the select voltage starts to change from its nominal value to its programming-enable value after the second voltage starts to change from its nominal value to its programming-inhibit value.

An erasable programmable read-only memory (“EPROM”) comprising:

• a group of memory elements respectively comprising like-polarity floating-gate field-effect transistors (“FETs”) wherein each FET comprises (a) first and second source/drain regions laterally separated from each other by a channel portion of a body region that forms a pn junction with each source/drain region, (b) a floating-gate electrode laterally adjacent to the first source/drain region and overlying a first part of the channel portion, and (c) a select-gate electrode laterally adjacent to the second source/drain region, spaced apart from the floating-gate electrode, and overlying a second part of the channel portion lateral to the first part of the channel portion, each FET being in an erased condition with a programmable threshold voltage (a) less than a first transition value VT1 if that FET is of n-channel type and (b) greater than −VT1 if that FET is of p-channel type, each FET being in a programmed condition when its programmable threshold voltage is (a) greater than a second transition value VT2 if that FET is of n-channel type and (b) less than −VT2 if that FET is of p-channel type where VT2 exceeds or equals VT1;
• first control circuitry which applies first voltages respectively to the first source/drain regions and is operable to change the first voltage for each FET from a nominal first value to a programming first value during a programming operation for that FET;
• second control circuitry which applies second voltages respectively to the second source/drain regions and is operable (a) to change the second voltage for each FET from a nominal second value to a programming second value during a programming operation for that FET if it is initially in its erased condition and is to remain in its erased condition during that programming operation and (b) to maintain the second voltage for each FET largely at the nominal value for that second voltage during the programming operation if that FET is to be placed in its programmed condition during that programming operation;
• and
• select-gate control circuitry which applies select voltages respectively to the select-gate electrodes and is operable to change the select voltage for each FET from a nominal select value to a programming select value during a programming operation for that FET such that, during a programming operation for a selected group of the FETs where each selected FET was in its erased condition prior to that programming operation, each selected FET (a) remains in its erased condition during that programming operation if its second voltage goes to the programming-inhibit value for that second voltage during that programming operation and (b) enters its programmed condition during that programming operation if its second voltage stays largely at the nominal value for that second voltage during that programming operation and such that, in an instance where one of the selected FETs is initially in its erased condition and is to remain in its erased condition, the select voltage for that selected FET starts changing from the nominal value for that select voltage to its programming-enable value after the second voltage for that selected FET starts changing from the nominal value for that second voltage to its programming-inhibit value.

A method comprising:

• providing a floating-gate field-effect transistor (“FET”) which comprises (a) first and second source/drain regions laterally separated from each other by a channel portion of a body region that forms a pn junction with each source/drain region, (b) a floating-gate electrode laterally adjacent to the first source/drain region and overlying a first part of the channel portion, and (c) a select-gate electrode laterally adjacent to the second source/drain region, spaced apart from the floating-gate electrode, and overlying a second part of the channel portion lateral to the first part of the channel portion, the FET being in an erased condition with a programmable threshold voltage (a) less than a first transition value VTI if the FET is of n-channel type and (b) greater than -VTI if the FET is of p-channel type, the FET being in a programmed condition when its programmable threshold voltage is (a) greater than a second transition value VT2 if the FET is of n-channel type and (b) less than -VT2 if the FET is of p-channel type where VT2 exceeds or equals VTI;
• providing first control circuitry for changing a first voltage applied to the first source/drain region from a nominal first value to a programming first value during a programming operation;
• providing second control circuitry (a) for changing a second voltage applied to the second source/drain region from a nominal second value to a programming-inhibit second value during a programming operation if the FET is initially in the erased condition and is to remain in the erased condition and (b) for maintaining the second voltage largely at the nominal second value during the programming operation if the FET is to be placed in its programmed condition;
• and
• providing select-gate control circuitry for changing a select voltage applied to the select-gate electrode from a nominal select value to a programming-enable select value during a programming operation such that, when the FET was in the erased condition prior to a programming operation, the FET (a) remains in the erased condition during that programming operation if the second voltage goes to its programming-inhibit value during that programming operation and (b) enters the programmed condition during that programming operation if the second voltage stays largely at its nominal value during that programming operation and such that, in an instance where the FET is to remain in the erased condition during a programming operation, the select voltage starts to change from its nominal value to its programming-enable value after the second voltage starts to change from its nominal value to its programming-inhibit value.

A method comprising:

• providing a group of like-polarity floating-gate field-effect transistors (“FETs”) wherein each FET comprises (a) first and second source/drain regions laterally separated from each other by a channel portion of a body region that forms a pn junction with each source/drain region, (b) a floating-gate electrode laterally adjacent to the first source/drain region and overlying a first part of the channel portion, and (c) a select-gate electrode laterally adjacent to the second source/drain region, spaced apart from the floating-gate electrode, and overlying a second part of the channel portion lateral to the first part of the channel portion, each FET being in an erased condition with a programmable threshold voltage (a) less than a first transition value VTI if that FET is of n-channel type and (b) greater than -VTI if that FET is of p-channel type, each FET being in a programmed condition when its programmable threshold voltage is (a) greater than a second transition value VT2 if that FET is of n-channel type and (b) less than -VT2 if that FET is of p-channel type where VT2 exceeds or equals VTI;
• providing first control circuitry (a) for applying first voltages respectively to the first source/drain regions and (b) for changing the first voltage for each FET from a nominal first value to a programming first value during a programming operation for that FET;
• providing second control circuitry (a) for applying second voltages respectively to the second source/drain regions, (b) for changing the second voltage for each FET from a nominal second value to a programming second value during a programming operation for that FET if it is initially in its erased condition and is to remain in its erased condition during that programming operation, and (c) for maintaining the second voltage for each FET largely at the nominal value for that second voltage during the programming operation if that FET is to be placed in its programmed condition during that programming operation;
• and
• providing select-gate control circuitry (a) for applying select voltages respectively to the select-gate electrodes, (b) for changing the select voltage for each FET from a nominal select value to a programming select value during a programming operation for that FET such that, during a programming operation for a selected group of the FETs where each selected FET was in its erased condition prior to that programming operation, each selected FET (i) remains in its erased condition during that programming operation if its second voltage goes to the programming-inhibit value for that second voltage during that programming operation and (ii) enters its programmed condition during that programming operation if its second voltage stays largely at the nominal value for that second voltage during that programming operation and such that, in an instance where one of the selected FETs is initially in its erased condition and is to remain in its erased condition, the select voltage for that selected FET starts changing from the nominal value for that select voltage to its programming-enable value after the second voltage for that selected FET starts changing from the nominal value for that second voltage to its programming-inhibit value.