Semiconductor memory device having an error correcting code circuit
AssigneeKabushiki Kaisha Toshiba
InventorOsamu Hirabayashi
Life of this patent
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Abstract
A semiconductor memory device include includes a memory cell array which includes a first group of rows and a second group of rows, each row of the first group consisting of a plurality of first memory cells whose layout direction is a first direction, and each row of the second group consisting of a plurality of second memory cells whose layout direction is different from the first direction, a plurality of word lines which select rows of the memory cell array and each of which is connected to the first memory cells and second memory cells, and a plurality of bit line pairs which select columns of the memory cell array.
Claims19
A semiconductor memory device comprising:
- a memory cell array which includes a first group of rows and a second group of rows, each row of the first group consisting of a plurality of first memory cells whose layout direction is a first direction, and each row of the second group consisting of a plurality of second memory cells whose layout direction is different from the first direction;
- a plurality of word lines which select rows of the memory cell array and each of which is connected to the first memory cells and second memory cells;
- and
- a plurality of bit line pairs which select columns of the memory cell array.
A semiconductor memory device comprising:
- a first memory cell array and a second memory cell array each of which has a plurality of memory cells arranged in a matrix;
- a plurality of first word lines each of which selects a row of the first memory cell array;
- a first row selection circuit which activates a corresponding one of the first word lines on the basis of a row address signal;
- a plurality of second word lines each of which selects a row of the second memory cell array;
- a second row selection circuit which activates a corresponding one of the second word lines on the basis of the row address signal;
- a plurality of first bit line pairs each of which selects a column of the first memory cell array;
- a plurality of second bit line pairs each of which selects a column of the second memory cell array;
- a first sense amplifier circuit which amplifies data transferred to the plurality of first bit line pairs;
- and
- a second sense amplifier circuit which amplifies data transferred to the plurality of second bit line pairs,
- wherein a distance between the second sense amplifier circuit and a second word line activated by the second row selection circuit is different from a distance between the first sense amplifier circuit and a first word line activated by the first row selection circuit.
A semiconductor memory device comprising:
- a first memory cell array and a second memory cell array each of which has a plurality of memory cells arranged in a matrix;
- a plurality of first word lines each of which selects a row of the first memory cell array;
- a plurality of second word lines each of which selects a row of the second memory cell array;
- a plurality of first bit line pairs each of which selects a column of the first memory cell array;
- a first column selection circuit which selects a corresponding one of the first bit line pairs on the basis of a column address signal;
- a plurality of second bit line pairs each of which selects a column of the second memory cell array;
- and
- a second column selection circuit which selects a corresponding one of the second bit line pairs on the basis of the column address signal,
- wherein when a column at an end of the first memory cell array is selected by the first column selection circuit, the second column selection circuit selects a column different from a column at an end of the second memory cell array.
Dependencies are inferred from the claim text.