Memory device capable of performing high speed reading while realizing redundancy replacement

A memory device comprising:

• a memory cell array, said memory cell array including
• a plurality of normal memory cells storing information by a change in electrical resistance value,
• spare memory cells arranged in a matrix together with said plurality of normal memory cells, placed in a central portion in said memory cell array, and each used instead of a defective memory cell when said defective memory cell exists among said plurality of normal memory cells,
• a plurality of bit lines placed along a column direction of said memory cell array, and for causing data read current to said plurality of normal memory cells,
• a spare bit line placed along said column direction, and for causing a data read current into said spare memory cells,
• a plurality of data lines transmitting a data read current flowing in a part of said plurality of bit lines and a data read current flowing in said spare bit line, and
• a connecting gate circuit not only connecting a selected bit line among said plurality of bit lines to be selected according to a data read command to one of said plurality of data lines, but also connecting said spare bit line to another one of said plurality of data lines;
• and
• a read amplifying circuit receiving a data read current transmitted by said plurality of data lines to read data in said plurality of normal memory cells and said spare memory cell.

A memory device comprising:

• a memory cell array, said memory cell array including
• a plurality of memory cells storing information by a change in electric resistance value,
• a plurality of source lines provided on paths through which read currents for reading data from said plurality of memory cells,
• dummy cells arranged in a matrix together with said plurality of memory cells, placed in a central portion of said memory cell array, and holding reference values for discriminating data in said plurality of memory cells,
• dummy source lines provided on paths through which reference currents for reading said reference values from said dummy cells flow, and
• a plurality of data lines transmitting said read currents and said reference currents;
• and
• a read amplifying circuit receiving read currents and reference currents transmitted by said plurality of data lines to read data in said plurality of memory cells.