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US 7,126,839 B2Granted
Nonvolatile ferroelectric memory cell and memory device using the same
AssigneeHynix Semiconductor Inc.
InventorHee Bok Kang
Life of this patent
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Abstract
A memory device using a nonvolatile ferroelectric memory cell stores processing results of various programs with a nonvolatile state in a nonvolatile ferroelectric register, and processes multiple data using a multi-port. In the memory device, various program processing results with a nonvolatile state are stored in a FeRAM register in a processing operation of a CPU (Central Processing Unit), thereby preventing destruction of the stored data even in a power-off mode. In addition, the multiple data are processed using a multi-port register, thereby improving reliability and operation speed.
Claims13
A nonvolatile ferroelectric memory cell which has multi write and multi read ports, comprising:
- a pull-up regulator for providing a power voltage in response to a pull-up enable signal;
- a first latch unit, cross-coupled between both storage nodes of the cell, for latching a power voltage applied from the pull-up regulator;
- a write port selector for selectively outputting data applied through a plurality of write bitline pairs into both storage nodes in response to each wordline driving signal applied through a plurality of write port wordlines;
- a ferroelectric capacitor unit for generating a voltage difference in both storage nodes in response to a cell plate signal, and for storing the data;
- a read port selector for selectively outputting data stored in the ferroelectric capacitor unit into a plurality of read bitline pairs in response to each wordline driving signal applied through a plurality of read port wordlines;
- a pull-down regulator for providing a ground voltage in response to a pull-down enable signal;
- and
- a second latch unit, cross-coupled between both storage nodes, for latching the ground voltage applied from the pull-down regulator.
5 more elements
A memory device using a nonvolatile ferroelectric memory cell, comprising:
- a plurality of memory cells connected to a pair of write bitlines and a plurality of read bitlines pairs, respectively, in row and column directions;
- a plurality of sense amplifiers connected to the plurality of read bitlines pairs;
- a plurality of wordline drivers connected to the pair of write bitlines;
- a pull-up regulator, connected in common to the plurality of memory cells connected in a row direction, for providing a power voltage to the plurality of memory cells in response to a pull-up enable signal;
- and
- a pull-down regulator, connected in common to the plurality of memory cells connected in the row direction, for providing a ground voltage to the plurality of memory cells in response to a pull-down enable signal,
- wherein each of the plurality of memory cells comprises:
- a write port selector for selectively outputting data applied through the pair of write bitlines into both storage nodes in response to a wordline driving signal applied through a write port wordline;
- a ferroelectric capacitor unit for generating a voltage difference in both storage nodes in response to a cell plate signal, and for storing the data;
- and
- a read port selector for selectively outputting data stored in the ferroelectric capacitor unit into the plurality of read bitline pairs in response to each wordline driving signal applied through a plurality of read port wordlines.
8 more elements
A memory device using a nonvolatile ferroelectric memory cell, comprising:
- a plurality of multi memory cells connected to a plurality of write bitline pairs and a plurality of read bitline pairs, respectively, in row and column directions;
- a plurality of sense amplifiers connected to the plurality of read bitline pairs, respectively;
- a plurality of wordline drivers connected to the plurality of write bitline pairs, respectively;
- a pull-up regulator, connected in common to the plurality of multi memory cells connected in the same row direction, for providing a power voltage to the plurality of multi memory cells in response to a pull-up enable signal;
- and
- a pull-down regulator, connected in common to the plurality of multi memory cells connected in the same row direction, for providing a ground voltage to the plurality of multi memory cells in response to a pull-down enable signal,
- wherein each of the plurality of multi memory cells comprises:
- a write port selector for selectively outputting data applied through the plurality of write bitline pairs into both storage nodes in response to a wordline driving signal applied through a plurality of write port wordlines;
- a ferroelectric capacitor unit for generating a voltage difference in both storage nodes in response to a cell plate signal, and for storing the data;
- and
- a read port selector for selectively outputting data stored in the ferroelectric capacitor unit into the plurality of read bitline pairs in response to a wordline driving signal applied through a plurality of read port wordlines.
8 more elements
A memory device using a nonvolatile ferroelectric memory cell, comprising:
- a nonvolatile ferroelectric register unit for storing data inputted through at least one or more write ports in response to a write control signal, and for sensing data outputted through at least one or more read ports in response to a read control signal;
- and
- a multi processor for performing a logic operation on data applied from at least one or more of the read ports, and for feedback inputting the operation results into at least one or more of the write ports,
- wherein the nonvolatile ferroelectric register unit comprises:
- a plurality of multi memory cells connected to a plurality of write bitline pairs and a plurality of read bitline pairs in row and column directions, respectively;
- a plurality of sense amplifiers connected to the plurality of read bitline pairs;
- a plurality of wordline driving units connected to the plurality of write bitline pairs;
- a pull-up regulator, connected in common to the plurality of multi memory cells connected in the same row direction, for providing a power voltage to the plurality of multi memory cells in response to a pull-up enable signal;
- and
- a pull-down regulator, connected in common to the plurality of multi memory cells connected in the same row direction, for providing a ground voltage to the plurality of multi memory cells in response to a pull-down enable signal,
- wherein each of the plurality of multi memory cells, which have multi write ports and multi read ports, comprises:
- a write port selector for selectively outputting data applied through the plurality of write bitline pairs into both storage nodes in response to each wordline driving signal applied through a plurality of write port wordlines;
- a ferroelectric capacitor unit for generating a voltage difference in both storage nodes in response to a cell plate signal, and for storing the data;
- and
- a read port selector for selectively outputting data stored in the ferroelectric capacitor unit into the plurality of read bitline pairs in response to each wordline driving signal applied through a plurality of read port wordlines.
12 more elements
Dependencies are inferred from the claim text.