Readout circuit, solid state image pickup device using the same circuit, and camera system using the same

A readout circuit comprising:

• a first signal readout unit comprising a first line memory comprising a plurality of memory units for holding signals, first switches each connected to each of said memory units of said first line memory, a first common signal line connected to a predetermined number of said first switches, and a second switch for connecting said first common signal line to a second common signal line, so as to selectively read out signals held in each memory unit of said first line memory on said second common signal line via at least one of said first switches, said first common signal line, and said second switch;
• a second signal readout unit comprising a second line memory comprising a plurality of memory units for holding signals, third switches each connected to each memory unit of said second line memory, a third common signal line connected to a predetermined number of said third switches, and a fourth switch for connecting said third common signal line to a fourth common signal line, so as to selectively read out signals held in each memory unit of said second line memory on said fourth common signal line via at least one of said third switches, said third common signal line, and said fourth switch;
• a processing unit for deriving a signal of difference between an output from said first signal readout unit and an output from said second signal readout unit;
• and
• a control unit for on/off controlling of said first and third switches, wherein
• said readout circuit comprises a first outgoing wiring provided between an electrode of said second switch and said second common signal line, a second outgoing wiring provided between an electrode of said fourth switch and said fourth common signal line, a first control wiring connected between said control unit and said first switches, and a second control wiring connected between said control unit and said third switches, and
• said first and second control wirings are arranged respectively at opposite sides of a center line between said first and second outgoing wirings.

A solid state image pickup device comprising a light receiving unit having a plurality of pixels, a line memory having a plurality of memory units holding temporarily signals from each of said pixels and a reading circuit for selectively reading the signals held by each of said memory units of said line memory, wherein said reading circuit comprises:

• a signal readout unit comprising first switches each connected to each memory unit of said line memory, a first common signal line connected to a predetermined number of said first switches, and a second switch for connecting said first common signal line to a second common signal line, so as to selectively read out signals held in each memory unit of said line memory on said second common signal line via at least one of said first switches, said first common signal line, and said second switch;
• a control unit for on/off controlling of said first and second switches;
• an outgoing wiring provided between an electrode of said second switch and said second common signal line;
• and
• control wiring connected between said control unit and at least one of said first and second switches, wherein
• said control wiring has a non-inversed signal supply wiring and an inversed signal supply wiring to which non-inversed and inversed signals of which logical levels are reversed each other are supplied, and
• said non-inversed signal supply wiring and said inversed signal supply wiring are arranged respectively at opposite sides of said outgoing wiring.

A solid state image pickup device comprising a light receiving unit having a plurality of pixels, a line memory having a plurality of memory units holding temporarily signals from each of said pixels and a reading circuit for selectively reading the signals held by each of said memory units of said line memory, wherein said reading circuit comprises:

• a first signal readout unit comprising a first line memory included in said line memory and disposed at a predetermined position, first switches each connected to each of memory units of said first line memory, a first common signal line connected to a predetermined number of said first switches, and a second switch for connecting said first common signal line to a second common signal line, so as to selectively read out signals held in each memory unit of said first line memory on said second common signal line via at least one of said first switches, said first common signal line, and said second switch;
• a second signal readout unit comprising a second line memory included in said line memory and disposed alternately adjacent to said first line memory, third switches each connected to each memory unit of said second line memory, a third common signal line connected to a predetermined number of said third switches, and a fourth switch for connecting said third common signal line to a fourth common signal line, so as to selectively read out signals held in each memory unit of said second line memory on said fourth common signal line via at least one of said third switches, said third common signal line, and said fourth switch;
• a control unit for on/off controlling said first and third switches;
• a first outgoing wiring provided between an electrode of said second switch and said second common signal line;
• a second outgoing wiring provided between an electrode of said fourth switch and said fourth common signal line;
• a first control wiring connected between said control unit and said first switches;
• and
• a second control wiring connected between said control unit and said third switches, wherein
• said first and second control wirings are arranged respectively at opposite sides of a center line between said first and second outgoing wirings.

A readout circuit comprising one or more layers of readout cells, each cell comprising a plurality of signal holding units including a plurality of signal holding cells, a common wiring for readout signals from said signal holding units, and a partially common wiring shared between two or more of said signal holding cells, wherein one unit of said readout cell contains said partially common wiring, said readout circuit comprising:

• an outgoing wiring for reading from said common wiring at a lower layer into said common wiring at an upper layer;
• and
• a control wiring disposed adjacent to said outgoing wiring,
• wherein said control wiring has a non-inversed signal supply wiring and an inversed signal supply wiring to which non-inversed and inversed signals of which logical levels are reversed with respect to each other are supplied, and
• said non-inversed signal supply wiring and said inversed signal supply wiring are arranged respectively at opposite sides of said outgoing wiring.