Interlocking memory/logic cell layout and method of manufacture
AssigneeNetLogic Microsystems, Inc.
InventorsBartosz Banachowicz, Andrew Wright
Life of this patent
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Abstract
A memory/logic cell layout structure includes a pair of memory/logic cells formed on a substrate. Each memory/logic cell (102, 104) can include a pair of memory areas to store data (106-0/106-1, 106-2/106-3), and a logic portion (108-0, 108-1) that receives the data stored therein. Memory areas and the logic portions of each memory/logic cell can be arranged on the substrate in a shape of an L, U, S, T, or Z to form a pair of interlocking memory/logic cells.
Claims21
A memory/logic cell layout structure, comprising:
- at least a first and second memory/logic cell, each memory/logic cell including a pair of memory areas and a logic circuit that receives data stored in the pair of memory areas;
- wherein
- the first memory/logic cell and second memory/logic cell are each bounded by a layout area and are interlocked with one another having layout areas that share at least two sides with one another.
A method of forming a memory/logic cell pairs on an integrated circuit substrate, comprising steps of:
- for each of a plurality of memory/logic cells, forming an identical layout for a plurality of device layers for memory areas and a logic section of each memory/logic cell;
- and
- forming at least a first and second memory/logic cell in a substrate according to the layout in interlocking positions, such that the memory/logic cells share at least two sides with one another.
Dependencies are inferred from the claim text.