Circuit arrangement for the delay adjustment of analog-to-digital converters operating in a temporally offset manner

A circuit arrangement for the delay adjustment of analog-to-digital converters operating in a temporally offset manner, having:

• (a) at least two analog-to-digital converters each having a signal path, which receive an analog signal present at an input of the circuit arrangement and in each case convert it into a digital intermediate signal, the analog-to-digital converters in each case being clocked by clock signals which have a predetermined time offset with respect to one another;
• (b) a logic circuit, which interconnects the digital intermediate signals for the purpose of generating a digital output signal of the circuit arrangement;
• it being possible to set the bandwidth of the signal paths of the analog-to-digital converters in each case in such a way that a deviation of the clock signal from the predetermined time offset for the respective analog-to-digital converter is compensated for by a change in the bandwidth of at least one signal path, wherein a second controllable switch, a buffer capacitor and a third controllable switch are provided between the control potential and the first reference potential, the controllable switches connecting the buffer capacitor either between the control potential terminal and the first reference potential or between the gate terminal of the transistor and the input of the means for bandwidth setting, depending on a control signal.

A circuit arrangement for the delay adjustment of analog-to-digital converters operating in a temporally offset manner, having:

• (a) at least two analog-to-digital converters each having a signal path, which receive an analog signal present at an input of the circuit arrangement and in each case convert it into a digital intermediate signal, the analog-to-digital converters in each case being clocked by clock signals which have a predetermined time offset with respect to one another;
• (b) a logic circuit, which interconnects the digital intermediate signals for the purpose of generating a digital output signal of the circuit arrangement;
• it being possible to set the bandwidth of the signal paths of the analog-to-digital converters in each case in such a way that a deviation of the clock signal from the predetermined time offset for the respective analog-to-digital converter is compensated for by a change in the bandwidth of at least one signal path, wherein at least one switch is provided between the gate terminal of the transistor and the switching potential, which switch switches either the switching potential or a control potential to the gate terminal depending on a control signal.

A circuit arrangement for the delay adjustment of analog-to-digital converters operating in a temporally offset manner, having:

• (a) at least two analog-to-digital converters each having a signal path, which receive an analog signal present at an input of the circuit arrangement and in each case convert it into a digital intermediate signal, the analog-to-digital converters in each case being clocked by clock signals which have a predetermined time offset with respect to one another;
• (b) a logic circuit, which interconnects the digital intermediate signals for the purpose of generating a digital output signal of the circuit arrangement;
• it being possible to set the bandwidth of the signal paths of the analog-to-digital converters in each case in such a way that a deviation of the clock signal from the predetermined time offset for the respective analog-to-digital converter is compensated for by a change in the bandwidth of at least one signal path, wherein at least one means for bandwidth setting has a transistor having a controllable path and a gate terminal, the controllable path being connected to the input of the means in the signal path and having a resistance depending on a control potential applied to the gate terminal.