Method for implementing a fractional sample rate converter (F-SRC) and corresponding converter architecture

An L:M Fractional Sample Rate Converter (F-SRC) architecture for controlled and direct insertion and cancellation of samples in a processed data stream, comprising:

• an up-sampler (1:P) input block receiving an input data stream and processing L signal samples (x(m)) having an input data rate (fIN) in a predetermined time interval (Ts), and providing an interpolated data stream upsampled by a factor P, P<M, therefore having a PfIN data rate;
• a rate adapting stage generating an intermediate data stream with signal samples (y1(k)) adapted to an intermediate data rate (PfOUT);
• and
• a low pass and decimation filter delivering an output data stream including M signal samples (z(n)) having a desired output sample rate (fOUT=M/Ts);
• the rate adapting stage weighting the signal samples (x1(h)) of the interpolated data stream;
• and
• the rate adapting stage adapting the input data rate to the output data rate by a direct insertion of zero samples into the processed stream when L<M, and by a direct cancellation of samples when L>M.

An L:M Fractional Sample Rate Converter (F-SRC) comprising:

• an up-sampler receiving an input data stream and processing L signal samples (x(m)) having an input data rate (fIN) in a predetermined time interval (Ts), and providing an interpolated data stream upsampled by a factor P, P<M, and having a PfIN data rate;
• a rate adapting stage weighting the signal samples (x1(h)) of the interpolated data stream and generating an intermediate data stream, the rate adapting stage adapting the input data rate to an output data rate by a direct insertion of zero samples into the data stream when L<M, and by cancellation of samples when L>M;
• and
• a decimation filter receiving the intermediate data stream and delivering an output data stream including M signal samples having the output data rate (fOUT=M/Ts).