Frequency synthesizer having a more versatile and efficient fractional-N control circuit and method
AssigneeCypress Semiconductor Corporation
InventorShuliang Li
Life of this patent
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Abstract
A frequency synthesizer is provided having a fractional-N control circuit and method that can selectively apply any fractional ratio to a frequency divider within the feedback loop of a PLL. A special digital delta-sigma modulator can be implemented as the control circuit and can receive any arbitrary numerator and denominator value, or their arithmetic combination, or a positive and negative vector values used by the modulator to achieve an average fractional division. Both the numerator and denominator (or the positive and negative vectors) can be chosen based on any integer value to achieve a more optimal, higher frequency resolution and efficient fractional-N control circuit and methodology thereof.
Claims19
A modulator circuit, comprising:
- at least one adder coupled to produce a sum value, a remainder value and a sign value;
- a multiplexer coupled to forward the sum value or the remainder value to the at least one adder depending on the sign value;
- and
- wherein the at least one adder comprises a multi-bit output from which the remainder value is produced, and wherein the most significant bit output of the multi-bit output is coupled to produce the sign bit.
A circuit for producing a signal of selectable frequency, comprising:
- a phase-locked loop having a divider that fractionally divides a frequency of the signal corresponding to a ratio of a numerator value and a denominator value;
- and
- a first adder coupled to receive the numerator value and a second adder coupled to receive an output from the first adder as well as the denominator value for producing a sign value in the most significant bit position output from the second adder that repeats to form a repeating binary bit pattern sent to the fractional divider for selecting the frequency of the signal based on the number of bits within the binary bit pattern and the number of bits within the binary bit pattern that are of a particular logic voltage.
A method of modifying a frequency of a signal, comprising:
- modulating a bit pattern from a sequence of signed binary numbers by extracting the signed binary numbers from a digital word and extracting the bit pattern from the most significant bit output of the digital word;
- defining a ratio of the number bit that are of one particular logic value within the bit pattern over the bit pattern length by changing a numerator value relative to a denominator value;
- and
- dividing the frequency of the signal based on the defined ratio.
Dependencies are inferred from the claim text.