Digital phase locked loop with selectable normal or fast-locking capability

A digital phase locked loop with selectable fast locking capability comprising:

• a digital controlled oscillator for producing an output clock phase locked to an input reference clock;
• a phase detector for measuring the phase difference between said input reference clock and a feedback clock;
• and
• a loop filter for producing a control signal for said digitally controlled oscillator, said loop filter comprising:
• a proportional circuit for developing a first signal proportional to said phase difference;
• an integrator for developing an integrated signal from said first signal;
• a weighting unit for selectively adding extra weight as a weighting factor in a fast locking mode to said first signal at an input to said integrator to cause said integrator to build up its contents more rapidly and thereby shorten the locking time of the phase locked loop, said weighting factor being in the form of a multiplier that multiples said first signal;
• and
• an adder for adding said first signal without said extra weight and said integrated signal developed by said integrator to develop said control signal for said digital controlled oscillator.