Method and corresponding circuit structure to correlate the transconductance of transistors of different types
AssigneeSimicroelectronics, S.R.L.
InventorsPietro Filoramo, Giovanni Calì
Life of this patent
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Abstract
A method and related circuit structure correlate the transconductance value of transistors of different type, for example MOS transistors and bipolar transistors. The structure comprises a first differential cell formed by transistors of the first type and a second differential cell formed by transistors of the second type connected to each other by means of a circuit portion responsible for calculating an error signal obtained as difference between the cell differential currents and applied to said first differential cell and to an output node of the same circuit structure obtaining a transconductance correlation independent from process tolerances and temperature.
Claims33
A method for correlating the transconductance value of transistors of different types, for example MOS transistors and bipolar transistors, wherein that it:
- provides a circuit structure comprising a first differential cell formed by transistors of the first type and a second differential cell formed by transistors of the second type;
- applies to the first and second differential cell, biased through respective queue currents, a constant differential voltage;
- draws an error signal related to the difference of the two differential currents by means of a circuit portion comprised in said circuit structure;
- and
- applies this error signal to said first differential cell and to an output node of the circuit structure drawing a transconductance correlation independent from process tolerances and temperature.
A circuit structure to correlate the transconductance value of transistors of different type, for example MOS transistors and bipolar transistors, wherein the circuit structure comprises a first differential cell formed by transistors of the first type and a second differential cell formed by transistors of the second type connected to each other by means of a circuit portion, comprised in said circuit structure, responsible for calculating an error signal as difference between the cell differential currents and applied to said first differential cell and to an output node of the same circuit structure obtaining a transconductance correlation independent from process tolerances and temperature.
A bias circuit, comprising:
- a first circuit including a first type of transistor and operable to receive a first bias signal and an input signal and to generate a first output signal in response to the input signal;
- a second circuit including a second type of transistor and operable to receive a second bias signal and the input signal and to generate a second output signal in response to the input signal;
- a first bias-signal generator operable to generate the second bias signal in response to a third bias signal;
- and
- a second bias-signal generator coupled to the first and second circuits and to the first bias-signal generator and operable to generate the third bias signal in response to the first and second output signals.
A bias circuit, comprising:
- a first differential pair of a first type of transistors having a bias node operable to receive a first bias current, first and second input nodes operable to receive a differential input voltage, and first and second output nodes;
- a second differential pair of a second type of transistors having a bias node, first and second input nodes operable to receive the differential input voltage, and first and second output nodes;
- a current mirror having an input node coupled to the first output node of the first differential pair and the second output node of the second differential pair and having an output node coupled to the second output node of the first differential pair and the first output node of the second differential pair;
- and
- a bias-current generator having a control node coupled to the output node of the current mirror and having an output node coupled to the bias node of the second differential pair.
An integrated circuit, comprising:
- a first circuit including a first type of transistor and operable to receive a first bias signal and an input signal and to generate a first output signal in response to the input signal;
- a second circuit including a second type of transistor and operable to receive a second bias signal and the input signal and to generate a second output signal in response to the input signal;
- a first bias-signal generator operable to generate the first bias signal;
- a second bias-signal generator operable to generate the second bias signal in response to a third bias signal;
- and
- a third bias-signal generator coupled to the first and second circuits and operable to generate the third bias signal in response to the first and second output signals.
An electronic system, comprising:
- an integrated circuit, comprising,
- a first circuit including a first type of transistor and operable to receive a first bias signal and an input signal and to generate a first output signal in response to the input signal,
- a second circuit including a second type of transistor and operable to receive a second bias signal and the input signal and to generate a second output signal in response to the input signal,
- a first bias-signal generator operable to generate the first bias signal,
- a second bias-signal generator operable to generate the second bias signal in response to a third bias signal, and
- a third bias-signal generator coupled to the first and second circuits and operable to generate the third bias signal in response to the first and second output signals.
A method, comprising:
- generating with a first type of transistor a first output signal in response to an input signal and a first bias signal;
- generating with a second type of transistor a second output signal in response to the input signal and a second bias signal;
- and
- adjusting the second bias signal to a level that causes the second output signal to equal the first output signal with a predetermined accuracy.
A method, comprising:
- biasing a first differential amplifier having transistors of a first type with a first bias signal;
- biasing a second differential amplifier having transistors of a second type with a second bias signal;
- generating a first output signal by amplifying an input signal with the first differential amplifier;
- generating a second output signal by amplifying the input signal with the second differential amplifier;
- comparing the first and second output signals;
- and
- adjusting the first bias signal in response to the comparison of the first and second output signals.
Dependencies are inferred from the claim text.