Method and device for generating a clock signal with predetermined clock signal properties
AssigneeKoninklijke Philips Electronics N.V.
InventorWolfgang Furtner
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Abstract
A method and device for generating a clock signal with predetermined clock signal properties firstly prepare a number of clock signals with an essentially identical frequency and with a respectively different phase relation with regard to a master clock signal in order to subsequently (on the basis of a control signal, which is prepared according to the clock signal to be generated), select predetermined clock signals from the number of prepared clock signals and to combine the selected clock signals in order to generate the desired clock signal.
Claims17
A method for generating at least one desired clock signal having predetermined clock signal properties, comprising the following steps:
- a) providing a plurality of clock signals having substantially the same frequency and respectively different phase relations each with respect to a master clock signal;
- (b) providing a control signal, the control signal including an enable signal sequence having a plurality of enable signals, wherein an enable signal for each of the plurality of clock signals is provided, and wherein the enable signal sequence indicates a frequency and a duty cycle of the desired clock signal to be generated;
- (c) on the basis of the control signal, selecting predetermined clock signals from the plurality of provided clock signals;
- and
- (d) combining the selected clock signals to generate the desired clock signal, and
- wherein each of the enable signals is provided delayed in order to set an alignment of each enable signal and the associated provided clock signal.
A device for generating at least one desired clock signal having a predetermined clock signal property, comprising:
- a multi-phase clock generator for providing a plurality of clock signals having substantially the same frequency and respectively different phase relations with respect to a master clock signal;
- and
- a phase overlay unit for receiving a control signal, the control signal including an enable signal sequence having a plurality of enable signals, wherein an enable signal for each of the plurality of clock signals is provided, and wherein the enable signal sequence indicates a frequency and a duty cycle of the desired clock signal to be generated,
- wherein the phase overlay unit selects predetermined clock signals from the plurality of provided clock signals on the basis of the control signal, and combines the selected clock signals to generate the desired clock signal,
- and wherein each of the enable signals is provided delayed in order to set an alignment of each enable signal and the associated provided clock signal.
Dependencies are inferred from the claim text.