Programmable logic device having an embedded differential clock tree

A clock distribution network in a programmable logic device (PLD), the clock distribution network comprising:

• a backbone clock signal line having a small signal differential clock signal;
• a small signal to rail-to-rail converter for converting the small signal differential clock signal to a rail-to-rail clock signal;
• and
• a plurality of branches coupled to the backbone clock signal line for distributing the small signal differential clock signal, after re-conversion to a small signal, to a plurality of programmable function elements on the PLD.

A system for providing a clock to an integrated circuit (IC) having configurable logic, comprising:

• a clock tree main trunk configured to provide a plurality of differential global clock signals to one or more circuits on the IC;
• a plurality of input circuits for receiving a plurality of external differential clock signals;
• a plurality of differential multiplexers for selecting an external clock signals of the plurality of external clock signals for sending to the clock tree main trunk, the plurality of differential multiplexers controlled by one or more configuration memory cells of the IC;
• and
• a plurality of multiplexers coupled between the plurality of differential multiplexers and the clock tree main trunk, the plurality of multiplexers selecting between the plurality of external clock signals and a plurality of upstream clock signals received from small signal to rail-to-rail converters.