High resolution digital delay circuit for PLL and DLL

A digital delay circuit comprising:

• means for providing a first delay;
• means for providing a second delay, said means for providing said second delay having a first input and a second input, wherein said first input is in communication with an output of said means for providing said first delay and wherein said second input is operative to receive a digital control signal for adjusting a time delay that said means for providing said second delay provides;
• means for receiving said output of said means for providing said first delay, an output of said means for providing said second delay and a control signal, wherein said control signal selects which of said output of said means for providing said first delay and said output of said means for providing said second delay is output by said means for receiving, wherein said output of said means for receiving is in communication with an input of said means for providing a first delay;
• means for obtaining an indication that a signal has cycled through a circuit loop comprising said means for receiving and said means for providing said first delay, wherein said indication is obtained from said output of said means for providing said second delay;
• means for incrementing a count each time said indication is received;
• and
• means for outputting, in response to said count being equal to a predetermined number, a signal that causes said output of said means for providing said second delay to be output by said means for receiving.

A method for providing an adjustable delay, said method comprising:

• providing a first delay;
• providing a second delay by introducing additional delay to said first delay, wherein said additional delay is digitally adjustable;
• receiving a first signal delayed by said first delay and a second signal delayed by said second delay;
• providing a control signal that selects which of said first signal and said second signal is selected, in response to receiving a signal delayed by one of said first and second delay steps;
• and
• delaying said selected signal by said first delay
• obtaining an indication from said second signal that a signal has cycled through a loop comprising said first delay;
• incrementing a count each time said indication is received;
• and
• outputting, in response to said count being equal to a predetermined number, a signal that causes said second signal to be selected.

A method for providing an adjustable delay, said method comprising;

• providing a first delay;
• providing a second delay by introducing additional delay to said first delay, wherein said additional delay is digitally adjustable;
• receiving a first signal delayed by said first delay and a second signal delayed by said second delay;
• receiving a control signal that selects which of said first signal and said second signal is selected
• obtaining an indication from said second signal that a signal has cycled through a loop comprising said first delay;
• incrementing a count each time said indication is received;
• and
• outputting, in response to said count being equal to a predetermined number, a signal that causes said second signal to be selected when said first signal and said second signal have the same logic value.

A method for providing an adjustable delay, said method comprising:

• providing a first delay;
• providing a second delay by introducing additional delay to said first delay, wherein said additional delay is digitally adjustable;
• receiving a first signal delayed by said first delay and a second signal delayed by said second delay;
• receiving a control signal that selects which of said first signal and said second signal is selected
• obtaining an indication that a signal has cycled through a loop comprising said first delay;
• incrementing a count each time said indication is received;
• and
• outputting, in response to said count being equal to a predetermined number, a signal that causes said second signal to be selected, wherein outputting said signal causes a signal to propagate through a loop comprising said second delay.