Delay adjustment circuit, integrated circuit device, and delay adjustment method

A delay adjustment circuit, comprising:

• a delay circuit to which an input signal is input, the delay circuit including a plurality of delay units and outputting a delay signal of the input signal;
• a comparison circuit which stores, to a comparison result register, comparison result data of a pulse width time of a pulse of a test input signal which is the input signal in a test mode and M-th to N-th (M and N are integers provided that N>M) delay times of M-th to N-th delay signals, the test input signal being input to the delay circuit and the M-th to N-th delay signals being respectively output from M-th to N-th taps among a plurality of taps provided between the delay units of the delay circuit;
• an adjustment circuit which adjusts delay time of the delay signal of the input signal in the delay circuit,
• wherein the comparison circuit includes first to (N−M+1)th logic circuits and the comparison result register which includes first to (N−M+1)th flip-flop circuits, and
• wherein the test input signal is input to a first input of each of the first to (N−M+1)th logic circuits, the M-th to N-th delay signals are respectively input to second inputs of the first to (N−M+1)th logic circuits, and outputs from the first to (N−M+1)th logic circuits are respectively input to clock terminals of the first to (N−M+1)th flip-flop circuits.

A delay adjustment circuit, comprising:

• a delay circuit to which an input signal is input, the delay circuit including a plurality of delay units and outputting a delay signal of the input signal;
• a comparison circuit which stores, to a comparison result register, comparison result data of a pulse width time of a pulse of a test input signal which is the input signal in a test mode and M-th to N-th (M and N are integers provided that N>M) delay times of M-th to N-th delay signals, the test input signal being input to the delay circuit and the M-th to N-th delay signals being respectively output from M-th to N-th taps among a plurality of taps provided between the delay units of the delay circuit;
• and
• an adjustment circuit which adjusts delay time of the delay signal of the input signal in the delay circuit,
• an initial state setting circuit which outputs adjustment data for adjusting the delay time of the delay signal of the input signal,
• wherein the adjustment circuit adjusts the delay time of the delay signal of the input signal based on the adjustment data output from the initial state setting circuit.