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US 7,126,399 B1Granted
Memory interface phase-shift circuitry to support multiple frequency ranges
AssigneeAltera Corporation
InventorAndy L. Lee
Life of this patent
Estimating the term…
Abstract
The present invention provides a phase shift circuit that supports multiple frequency ranges. The phase shift circuit receives a plurality of control bits and causes a phase shift in a received signal, the phase shift corresponding to a number of time steps, the number depending on the control bits, and the time step is selected from a plurality of different time steps based on a frequency range associated with the received signal.
Claims16
An intergrated circuit comprising:
- a plurality of programmable logic elements, configurable to implement user-defined logic functions;
- a double data-rate register coupled to the plurality of programmable logic elements and having data and clock inputs and comprising:
- a first storage circuit having a data input coupled to the data input of the double data-rate register;
- a second storage circuit having a data input coupled to the data input of the double data-rate register;
- and
- a third storage circuit having a data input coupled to the an output of the second storage circuit;
- a first delay element to provide a delay between a signal at the data input of the double data-rate register and a signal at the clock input of the double data-rate register, the first delay element comprising:
- a first delay circuit;
- a second delay circuit;
- and
- a multiplexer having a first input coupled to an output of the first delay circuit and a second input coupled to an output of the second delay circuit;
- and
- a control circuit coupled to adjust the delay provided by the first delay element, the control circuit comprising;
- a second delay element comprising:
- a first delay circuit;
- a second delay circuit;
- and
- a multiplexer having a first input coupled to an output of the first delay circuit and a second input coupled to an output of the second delay circuit;
- and
- a control logic circuit.
17 more elements
An integrated circuit comprising:
- a plurality of programmable logic elements, configurable to implement user-defined logic functions;
- a double data-rate register having a data input responsive to a signal received at a pad, a clock input, and comprising:
- a first flip-flop having a data input coupled to the data input of the double data-rate register;
- and
- a second flip-flop having a data input coupled to the data input of the double data-rate register;
- a first delay block coupled to provide a phase delay between a signal at the data input of the double data-rate register and a signal at the clock input of the double data-rate register, the first delay block comprising:
- a first delay element;
- a second delay element;
- and
- a multiplexer having a first input coupled to an output of the first delay element and a second input coupled to an output of the second delay element;
- and
- a control circuit coupled to control the phase delay provided by the first delay block, the control circuit comprising;
- a second delay block comprising:
- a first delay element;
- a second delay element;
- and
- a multiplexer having a first input coupled to an output of the first delay element and a second input coupled to an output of the second delay element.
14 more elements
An integrated circuit comprising:
- a plurality of programmable logic elements, configurable to implement user-defined logic functions;
- a double data-rate register coupled to the plurality of programmable logic elements and having a data input responsive to a signal received at a first pad, a clock input, and comprising:
- a first storage circuit having a data input coupled to the data input of the double data-rate register;
- a second storage circuit having a data input coupled to the data input of the double data-rate register;
- and
- a third storage circuit having a data input coupled to the an output of the second storage circuit;
- an input circuit having an input coupled to a second pad and an output coupled to the clock input of the double data-rate register;
- and
- a delay element to provide a phase delay between a signal at the data input of the double data-rate register and a signal at the clock input of the double data-rate register, the delay element comprising:
- a first delay circuit;
- a second delay circuit;
- and
- a multiplexer having a first input coupled to an output of the first delay circuit and a second input coupled to an output of the second delay circuit.
10 more elements
An integrated circuit comprising:
- a plurality of programmable logic elements, configurable to implement user-defined logic functions;
- a double data-rate register coupled to the plurality of programmable logic elements and having a data input responsive to a signal received at a first pad, a clock input, and comprising:
- a first storage circuit having a data input coupled to the data input of the double data-rate register;
- a second storage circuit having a data input coupled to the data input of the double data-rate register;
- and
- a third storage circuit having a data input coupled to an output of the second storage circuit;
- an input circuit having an input coupled to a second pad and an output coupled to the clock input of the double data-rate register;
- a delay element to provide a phase delay between a signal at the data input of the double data-rate register and a signal at the clock input of the double data-rate register, the delay element comprising:
- a first delay circuit;
- a second delay circuit;
- and
- a multiplexer having a first input coupled to an output of the first delay circuit and a second input coupled to an output of the second delay circuit;
- and
- a control circuit comprising:
- a counter, wherein the counter is incremented or decremented to adjust the phase delay provided by the delay element.
12 more elements
Dependencies are inferred from the claim text.