Pulse width modulation carrier frequency technique

A circuit for generating pulse-width modulated signal, comprising:

• temporary pulse-width modulated (PWM) generation logic that generates a temporary PWM signal comprising analog duty cycle information adapted for a first frequency;
• conversion logic coupled to said temporary PWM generation logic and that converts at least a portion of said analog duty cycle information to digital duty cycle information adapted for a second frequency;
• and
• final PWM generation logic coupled to said conversion logic and that generates a final PWM signal from said digital duty cycle information, said final PWM having a carrier frequency of said second frequency.

A circuit for generating a pulse-width modulated signal, comprising:

• a ramp voltage generator that is operable to generate a ramped voltage having a first frequency that has a user-specified relationship to a master clock;
• a comparator having a first input coupled to said ramp voltage generator output, a second input that receives an input signal, and an output that outputs a temporary pulse width modulated (PWM) signal comprising analog duty cycle information;
• down-sampling logic coupled to said comparator output and that selects portions of said analog duty cycle information;
• and
• duty cycle conversion logic coupled to said down-sampling logic and that converts said selected portions of said analog duty cycle information cycle to digital duty cycle information adapted for said down-sampled frequency;
• and
• PWM generation logic coupled to said conversion logic and that generates a final PWM signal from said digital duty cycle information, said final PWM having a carrier frequency of said down-sampled frequency.