History-based slew rate control to reduce intersymbol interference
AssigneeMicron Technology, Inc.
InventorEbrahim H. Hargan
Life of this patent
Estimating the term…
Abstract
In one aspect of the invention, a method of reducing intersymbol interference on a signal line is disclosed. A state machine records previous bits that were transmitted over the line. If the bit on the line has been static for several clock cycles, the slew rate will be increased to facilitate correct reading of the bit for the next clock cycle. If the bit on the line has been dynamic for the previous bits, the slew rate will be a lower slew rate to avoid crosstalk between neighboring lines.
Claims22
A method of increasing bit valid time on a signal line comprising:
- tracking values of a sequence of bits transmitted on a signal line;
- determining a current state of the signal line based on the values of a selected number of most recently received bits in the sequence;
- and
- adjusting with a controller a slew rate of a driving device of the signal line in response to the current state of the signal line and in response to a value of a next bit in the sequence of bits, the controller comprising at least one delay element, at least one output buffer and a multiplexer.
An integrated circuit comprising:
- a transmission line that communicates a sequence of data bits;
- a state machine that monitors the sequence of data bits, determining a line state based on at least two most recent bits in the sequence, and that outputs a slew rate control signal based on the line state and a next bit in the sequence of bits;
- and
- a slew rate controller that adjusts a rate of change of voltage on the transmission line based upon the slew rate control signal, the slew rate controller comprising a first slew rate control signal generator, a second slew rate control signal generator and a third slew rate control signal generator,
- wherein the second slew rate control signal generator further comprises a plurality of delay elements, a plurality of output buffers and a multiplexer.
A system for increasing bit valid time on a memory device signal line, the system comprising:
- a state machine to record a previous state of a memory device signal line based on values of at least two recent data bits transmitted on the signal line;
- a driving circuit to transmit a signal down the signal line;
- and
- a slew rate controller for adjusting the resistance of the driving circuit based at least in part on a comparison between a value of a current bit and the values of the at least two recent bits, the slew rate controller comprising a plurality of control signal generators, each control signal generator comprising at least one delay element, at least one output buffer and a multiplexer.
Dependencies are inferred from the claim text.