Lower power high speed design in BiCMOS processes
AssigneeIntel Corporation
InventorUlrich Dieter Felix Keil
Life of this patent
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Abstract
A low power high-speed design for integrated circuits using BiCMOS processes is disclosed. The design uses a first stage including bipolar transistor pairs configured as inputs and drivers for an output. A second CMOS stage is coupled to the first stage in a series-gated configuration and receives clock or data inputs. A third stage is coupled to the second stage and is configured as a current source. The combination results in circuits that can operate at conventional supply voltages of 1.8 volts.
Claims35
An integrated circuit, comprising:
- a first differential pair of bipolar transistors to drive a next stage;
- a second differential pair of bipolar transistors;
- a first CMOS transistor coupled to the first differential pair in a cascode configuration;
- a second CMOS transistor coupled to the second differential pair, the first CMOS transistor to receive a first clock signal and the second CMOS transistor to receive a second clock signal, the second clock signal being a differential of the first clock signal;
- and
- a third transistor coupled to the first CMOS transistor and the second CMOS transistor, the third transistor configured as a current source.
An apparatus comprising:
- a first bipolar stage to receive an input and drive a subsequent stage;
- a second CMOS stage coupled to the first bipolar stage in a series-gated configuration, the second CMOS stage including a first CMOS transistor to receive a first clock signal and a second CMOS transistor to receive a second clock signal, the first and second clock signals being a differential pair;
- and
- a third stage coupled to the second CMOS stage in a series-gated configuration, the third stage to operate as a current source.
A BiCMOS latch comprising:
- a first transistor and a second transistor configured as a differential pair coupled to a differential input and to a differential output, and the first and second transistors are bipolar transistors;
- a third transistor and a fourth transistor configured as a differential pair having bases and collectors coupled to opposite sides of the differential output, and the third and fourth transistors are bipolar transistors;
- a fifth transistor to receive a first clock input and a sixth transistor to receive a second clock input, the first and second clock inputs being a differential pair, the fifth and sixth transistors are CMOS transistors, the fifth transistor is coupled to the first and second transistors and the sixth transistor is coupled to the third and fourth transistors in a series-gated configuration;
- and
- a seventh transistor coupled to the fifth and sixth transistors, and the seventh transistor to operate as a current source.
An integrated circuit, comprising:
- a first differential pair of bipolar transistors to drive a next stage;
- a second transistor coupled to the first differential pair in a cascode configuration, the second transistor comprising a CMOS transistor;
- a third transistor coupled to the second transistor, the third transistor configured as a current source;
- and
- a level shifter coupled to the second transistor.
An apparatus comprising:
- a first differential pair of bipolar transistors to drive a next stage;
- a second CMOS stage coupled to the first bipolar stage in a series-gated configuration;
- a third stage coupled to the second CMOS stage in a series-gated configuration, and the third stage to operate as a current source;
- and
- a level shifter coupled to the second CMOS stage, and the level shifter to buffer a differential pair of clock inputs.
Dependencies are inferred from the claim text.