Transceiver providing high speed transmission signal using shared resources and reduced area
AssigneeSTMicroelectronics Pvt. Ltd.
InventorHari B. Dubey
Life of this patent
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Abstract
A transceiver provides a high-speed transmission signal using shared resources and reduced area. A differential amplifier has its current source/sink connected to a supply terminal. A multiplexing circuit is configured to connect an input of the differential amplifier to an I/O pad so as to output a received input/output signal to internal integrated circuit logic during one mode, or alternatively connect an output of the differential amplifier to the I/O pad so as to output a signal received from the internal integrated circuit logic for input/output during another mode. A level translation operation on the signal may be performed with respect to outputting the signal received from the internal integrated circuit logic.
Claims28
A transceiver providing a high-speed transmission signal using shared resources and reduced area, comprising:
- a differential amplifier having its current source/sink connected to a supply terminal, and
- a multiplexer configured to connect in a first mode an input of the differential amplifier to an I/O pad so as to generate internal integrated circuit logic signals from input/output signals during a receive mode, and connect in a second mode an output of the differential amplifier to the I/O pad so as to generate input/output signals from internal integrated circuit logic signals during a transmit mode.
A method for providing a transceiver enabling a high-speed transmission signal comprising the steps of:
- connecting a current source/sink of a differential amplifier to a supply terminal;
- configuring a multiplexer for connecting an input of the differential amplifier to an I/O pad so as to generate internal integrated circuit logic signals from input/output signals during a receive mode, and for connecting an output of the differential amplifier to the I/O pad so as to generate input/output signals from internal integrated circuit logic signals during a transmit mode, and
- configuring the current source/sink by a selector to receive bias from a voltage divider network for switching to a higher voltage level during transmit mode and to a lower voltage level during receive mode.
A transceiver circuit that interfaces an integrated circuit core input node, an integrated circuit core output node and an integrated circuit input/output node, comprising:
- a multiplexer having a first input for connection to the input/output node and a second input for connection to the core output node, the multiplexer having an output that is connected to the first input in a first mode and to the second input in a second mode;
- a selectable level shifting circuit having an input connected to the multiplexer output, the level shifting circuit performing signal level shifting of received core output node signals in the second mode but no signal level shifting of received input/output node signals in the first mode;
- a first transmission circuit having an input for connection to the level shifting circuit output and an output for connection to the core input node, the first transmission circuit operable to make an input to output connection for delivery of input/output node signals when in the first mode;
- and
- a second transmission circuit having an input for connection to the level shifting circuit output and an output for connection to the input/output node, the second transmission circuit operable to make an input to output connection for delivery of level shifted core output node signals when in the second mode.
A method for interfacing an integrated circuit core input node, an integrated circuit core output node and an integrated circuit input/output node, comprising:
- selecting an input/output node signal from the input/output node in a first mode;
- selecting a core output signal from the core output node in a second mode;
- passing the selected input/output signal or core output signal through a selectable level shifting circuit and performing signal level shifting on the core output signal in the second mode but no signal level shifting of the input/output signal in the first mode;
- transmitting the input/output signal from the selectable level shifting circuit to the core input node when in the first mode;
- and
- transmitting the level shifted core output signal from the selectable level shifting circuit to the input/output node when in the second mode.
Dependencies are inferred from the claim text.