Method, apparatus, and article of manufacture for manufacturing high frequency balanced circuits

A system for optimizing a balanced circuit comprising

• means for obtaining S-parameters for the balanced circuit, said balanced circuit comprising at least four single-ended terminals,
• a processor that determines a delay value such that a delay line substantially having said delay value that is embedded at one of said single-ended terminals minimizes a differential to common mode conversion mixed-mode transmission S-parameter for said balanced circuit in combination with said delay line substantially having said delay value.

An article of manufacture comprising computer readable storage media including computer software embedded therein that causes a processing unit to perform the method comprising the steps of:

• obtaining S-parameters for a balanced circuit said balanced circuit comprising at least four single-ended terminals, and determining a delay value embedded at one of said single-ended terminals of said balanced circuit that reduces a magnitude of a differential to common mode conversion mixed-mode transmission S-parameter for said balanced circuit in combination with a loss-less delay line having said delay value.