Semiconductor device having a capacitance device

A semiconductor device comprising an isolation region formed in a semiconductor layer, a capacitance device formed above the isolation region, and a second contact section connected to the capacitance device;

• the capacitance device including:
• a first capacitor conductive layer disposed above the isolation region, and
• a second capacitor conductive layer formed along one side surface of the first capacitor conductive layer,
• the second capacitor conductive layer being disposed facing the first capacitor conductive layer, with a first capacitor insulating layer interposed;
• the second contact section including a fourth contact conductive layer and a fifth contact conductive layer;
• the fourth contact conductive layer being connected to the first capacitor conductive layer;
• and
• the fifth contact conductive layer being connected to the second capacitor conductive layer.

A semiconductor device comprising an isolation region formed in a semiconductor layer, a capacitance device formed above the isolation region, a first contact section connected to the capacitance device, and a second contact section connected to the capacitance device,

• the capacitance device including:
• a first capacitor conductive layer disposed above the isolation region, and
• a second capacitor conductive layer formed along one side surface of the first capacitor conductive layer,
• the second capacitor conductive layer being disposed facing the first capacitor conductive layer, with a first capacitor insulating layer interposed;
• the first contact section including a first contact conductive layer and a pad-shaped second contact conductive layer disposed above the first contact conductive layer;
• the second contact section including a fourth contact conductive layer and a fifth contact conductive layer;
• the fourth contact conductive layer being connected to the first capacitor conductive layer;
• and
• the fifth contact conductive layer being connected to the second capacitor conductive layer.

A semiconductor device comprising an isolation region formed in a semiconductor layer and a capacitance device formed above the isolation region,

• the capacitance device including:
• a first capacitor conductive layer disposed above the isolation region,
• a second capacitor conductive layer formed along one side surface of the first capacitor conductive layer,
• the second capacitor conductive layer being disposed facing the first capacitor conductive layer, with a first capacitor insulating layer interposed;
• a contact region formed of a doped layer being further provided in the semiconductor layer, and
• the contact region being disposed around the isolation region.

A semiconductor device comprising an isolation region formed in a semiconductor layer and a capacitance device formed above the isolation region,

• the capacitance device including:
• a first capacitor conductive layer disposed above the isolation region,
• a second capacitor conductive layer formed along one side surface of the first capacitor conductive layer,
• the second capacitor conductive layer being disposed facing the first capacitor conductive layer, with a first capacitor insulating layer interposed;
• the semiconductor device further comprising a memory cell array in which non-volatile memory cells are arranged in a matrix of rows and columns,
• each of the non-volatile memory cells including:
• a word gate provided above the semiconductor layer with a first gate insulating layer interposed;
• an impurity layer formed in the semiconductor layer, to configure a source region or drain region;
• and
• first and second control gates provided along one side surface and another side surface of the word gate, respectively;
• the first control gate being disposed facing the semiconductor layer with a second gate insulating layer interposed, and also facing the word gate with a second side insulating layer interposed;
• and
• the second control gate being disposed facing the semiconductor layer with the second gate insulating layer interposed, and also facing the word gate with the second side insulating layer interposed.