Integrated circuits with contemporaneously formed array electrodes and logic interconnects
AssigneeMicron Technology, Inc.
InventorsMirmajid Seyyedy, Glen E. Hush, Mark E. Tuttle, Terry C. Vollman
Life of this patent
Estimating the term…
Abstract
The invention relates to interconnects for an integrated circuit memory device. Embodiments of the invention include processes to fabricate interconnects for memory devices in relatively few steps. Embodiments of the invention further include memory devices with metallization layers having unequal pitch dimensions in different areas of the chip, thereby permitting simultaneous fabrication of array electrodes and electrical interconnects in different areas of the chip. This reduces the number of fabrication steps used to make interconnects, thereby speeding up fabrication and reducing production costs.
Claims23
An integrated circuit memory device comprising:
- a semiconductor substrate assembly;
- a memory array with a plurality of memory cells disposed above the semiconductor substrate assembly;
- a plurality of metallization layers disposed above the substrate assembly, where at least one metallization layer is configured to provide electrodes for memory cell storage devices of the memory array and is also configured to provide interconnects for a logic circuit area, wherein the electrodes and the interconnects in the same metallization layer further include cladding of a magnetic material to form magnetic keepers;
- and
- a plurality of interlayer dielectric layers disposed between metallization layers.
An integrated circuit memory device comprising:
- a semiconductor substrate assembly;
- a memory array with a plurality of memory cells disposed above the semiconductor substrate assembly;
- a plurality of metallization layers disposed above the substrate assembly, where at least one metallization layer is configured to provide electrodes for memory cells of the memory array and is also configured to provide interconnects for a logic circuit area, wherein the memory cells are magnetoresistive random access memory (MRAM) cells, wherein the electrodes and the interconnects in the same metallization layer further include cladding of a magnetic material to form magnetic keepers;
- and
- a plurality of interlayer dielectric layers disposed between metallization layers.
An integrated circuit memory device comprising:
- a semiconductor substrate assembly;
- a memory array with a plurality of memory cells disposed above the semiconductor substrate assembly wherein the memory cell storage devices are programmable conductor random access memory (PCRAM) cell storage devices;
- a plurality of metallization layers disposed above the substrate assembly, where at least one metallization layer is configured to provide electrodes for memory cell storage devices of the memory array and is also configured to provide interconnects for a logic circuit area;
- and
- a plurality of interlayer dielectric layers disposed between metallization layers.
An integrated circuit memory device comprising:
- a semiconductor substrate assembly;
- a memory array with a plurality of memory cells disposed above the semiconductor substrate assembly;
- a plurality of metallization layers disposed above the substrate assembly, where at least one metallization layer is configured to provide electrodes for memory cells of the memory array and is also configured to provide interconnects for a logic circuit area;
- and
- a plurality of interlayer dielectric layers disposed between metallization layers;
- and
- a pitch circuit area disposed at least between the memory array and the logic circuit area, where the metallization layer in the pitch circuit area includes interconnects to the memory array, and where at least a portion of the interconnects in the pitch circuit area have the same pitch as the electrodes in the memory array.
Dependencies are inferred from the claim text.