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US 7,126,185 B2Granted
Charge trap insulator memory device
AssigneeHynix Semiconductor Inc.
InventorsHee Bok Kang, Jin Hong Ahn, Jae Jin Lee
Life of this patent
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Abstract
A charge trap insulator memory device comprises a plurality of memory cells connected serially, a first switching device, and a second switching device. In the plurality of memory cells, data applied through a bit line depending on potentials applied to a top word line and a bottom word line are stored in a charge trap insulator or the data stored in the charge trap insulator are outputted to the bit line. The first switching element selectively connects the plurality of memory cells to the bit line in response to a first selecting signal. The second switching element selectively connects the plurality of memory cells to a sensing line in response to a second selecting signal.
Claims26
A charge trap insulator memory device comprising:
- a bottom word line;
- a first insulating layer formed on the bottom word line;
- a P-type float channel formed on the first insulating layer and kept at a floating state;
- a second insulating layer formed on the P-type float channel;
- a charge trap insulator, formed on the second insulating layer, where charges are stored;
- a third insulating layer formed on the charge trap insulator;
- a top word line formed on the third insulating layer;
- and
- a P-type drain region and a P-type source region formed at both sides of the P-type float channel,
- wherein data are written in the charge trap insulator by a voltage difference of the top word line and the float channel, and
- data are read according to different channel resistance induced to the float channel depending on polarity states of charges stored in the charge trap insulator while a positive read voltage is applied to the bottom word line.
8 more elements
A charge trap insulator memory device comprising:
- a plurality of unit memory cell arrays each including a plurality of charge trap insulator memory cells and deposited as a multiple layer,
- wherein the charge trap insulator memory cell comprises:
- a bottom word line;
- a first insulating layer formed on the bottom word line;
- a P-type float channel formed on the first insulating layer and kept at a floating state;
- a second insulating layer formed on the P-type float channel;
- a charge trap insulator, formed on the second insulating layer, where charges are stored;
- a third insulating layer formed on the charge trap insulator;
- a top word line formed on the third insulating layer;
- and
- a P-type drain region and a P-type source region formed at both sides of the float channel,
- wherein data are written in the charge trap insulator by a voltage difference of the top word line and the float channel, and
- data are read according to different channel resistance induced to the float channel depending on polarity states of charges stored in the charge trap insulator while a positive read voltage is applied to the bottom word line.
10 more elements
A charge trap insulator memory device comprising:
- a plurality of memory cells connected serially where data applied through a bit line depending on potentials applied to a top word line and a bottom word line are stored in a charge trap insulator or the data stored in the charge trap insulator are outputted to the bit line;
- a first switching element for selectively connecting the plurality of memory cells to the bit line in response to a first selecting signal;
- and
- a second switching element for selectively connecting the plurality of memory cells to a sensing line in response to a second selecting signal,
- wherein each of the plurality of memory cells comprises:
- a first insulating layer formed on the bottom word line;
- a P-type float channel, formed on the first insulating layer, whose resistance is changed depending on the polarity of the charge trap insulator;
- a P-type drain region and a P-type source region formed at both sides of the P-type float channel;
- a second insulating layer formed on the P-type float channel;
- the charge trap insulator formed on the second insulating layer;
- and
- a third insulating layer formed on the charge trap insulator and under the top word line.
9 more elements
A charge trap insulator memory device comprising:
- a plurality of top word lines and a plurality of bottom word lines arranged in parallel to each other and in a row direction;
- a plurality of bit lines arranged in a column direction;
- a plurality of sensing lines arranged perpendicular to the plurality of bit lines;
- a plurality of memory cell arrays arranged where the plurality of top word lines, the plurality of bottom word lines and the plurality of bit lines are crossed;
- and
- a plurality of sense amplifiers, corresponding one by one to the plurality of bit lines, for sensing and amplifying data in the bit line,
- wherein each of the plurality of memory cell arrays comprises:
- a plurality of serially connected memory cells where data applied through a bit line are stored in a charge trap insulator depending on potentials applied to a top word line and a bottom word line or data stored in the charge trap insulator are outputted to the bit line;
- a first switching element for selectively connecting the plurality of memory cells to a bit line in response to a first selecting signal;
- and
- a second switching element for selectively connecting the plurality of memory cells to a sensing line in response to a second selecting signal,
- wherein each of the plurality of memory cells comprises:
- a first insulating layer formed on the bottom word line;
- a P-type float channel, formed on the first insulating layer, whose resistance is changed depending on the polarity of the charge trap insulator;
- a P-type drain region and a P-type source region formed at both sides of the P-type float channel;
- a second insulating layer formed on the P-type float channel;
- the charge trap insulator formed on the second insulating layer;
- and
- a third insulating layer formed on the charge trap insulator and under the top word line.
16 more elements
The charge trap insulator memory device according to 19, wherein a ground voltage is connected to the top word line of the other memory cells than the selected memory cell.
Dependencies are inferred from the claim text.