Programmable array logic or memory with p-channel devices and asymmetrical tunnel barriers

A flash memory array, comprising:

• a number of p-channel depletion mode, non-volatile memory cells, wherein each non-volatile memory cell includes:
• a first source/drain region and a second source/drain region separated by a depletion mode p-channel region;
• a floating gate opposing the p-channel region and separated therefrom by a gate oxide;
• a control gate opposing the floating gate;
• and
• wherein the control gate is separated from the floating gate by an asymmetrical low tunnel barrier intergate insulator having a number of small compositional ranges such that gradients can be formed which produce different barrier heights at an interface with the floating gate and control gate;
• a number of sourcelines coupled to the first source/drain regions along a first selected direction in the flash memory array;
• a number of control gate lines coupled to the control gates along a second selected direction in the flash memory array;
• and
• a number of bitlines coupled to the second source/drain regions along a third selected direction in the flash memory array;
• wherein the floating gate includes a polysilicon floating gate having a metal layer formed thereon in contact with the asymmetrical low tunnel barrier intergate insulator;
• wherein the control gate includes a polysilicon control gate having a metal layer formed thereon in contact with the asymmetrical low tunnel barrier intergate insulator, wherein the metal layer formed on the polysilicon control gate includes a metal layer that has a different work function than the metal layer formed on the floating gate;
• and
• wherein metal layer formed on the floating gate includes a parent metal for the asymmetrical low tunnel barrier intergate insulator and the metal layer formed on the control gate includes a metal layer having a work function in the range of 2.7 eV to 5.8 eV.

An array of flash memory cells, comprising:

• a number of pillars extending outwardly from a substrate, wherein each pillar includes a first source/drain region, a body region having a p-type channel, and a second source/drain region;
• a number of floating gates opposing the body regions in the number of pillars and separated therefrom by a gate oxide;
• a number of control gates opposing the floating gates;
• a number of buried sourcelines disposed below the number of pillars and coupled to the first source/drain regions along a first selected direction in the array of memory cells;
• a number of control gate lines formed integrally with the number of control gates along a second selected direction in the array of flash memory cells, wherein the number of control gates are separated from the floating gates by a low tunnel barrier intergate insulator having a number of small compositional ranges such that gradients can be formed by an applied electric field which produce different barrier heights at an interface with the floating gate and control gate;
• and
• a number of bitlines coupled to the second source/drain regions along a third selected direction in the array of flash cells.

An array of flash memory cells, comprising:

• a number of pillars extending outwardly from a substrate, wherein each pillar includes a first source/drain region, a body region having a p-type channel, and a second source/drain region;
• a number of floating gates opposing the body regions in the number of pillars and separated therefrom by a gate oxide;
• a number of control gates opposing the floating gates;
• a number of buried sourcelines disposed below the number of pillars and coupled to the first source/drain regions along a first selected direction in the array of memory cells;
• a number of control gate lines formed integrally with the number of control gates along a second selected direction in the array of flash memory cells, wherein the number of control gates are separated from the floating gates by a low tunnel barrier intergate insulator having a number of small compositional ranges such that gradients can be formed by an applied electric field which produce different barrier heights at an interface with the floating gate and control gate;
• and
• a number of bitlines coupled to the second source/drain regions along a third selected direction in the array of flash cells;
• wherein each floating gate includes a polysilicon floating gate having a metal layer formed thereon in contact with the asymmetrical low tunnel barrier intergate insulator;
• wherein each control gate includes a polysilicon control gate having a metal layer formed thereon in contact with the low tunnel barrier intergate insulator, wherein the metal layer formed on the polysilicon control gate includes a metal layer that has a different work function than the metal layer formed on the floating gate;
• and
• wherein metal layer formed on the floating gate includes a parent metal for the asymmetrical low tunnel barrier intergate insulator and the metal layer formed on the control gate includes a metal layer having a work function in the range of 2.7 eV to 5.8 eV.

An array of flash memory cells, comprising:

• a number of pillars extending outwardly from a substrate, wherein each pillar includes a first source/drain region, a body region having a p-type channel, and a second source/drain region;
• a number of floating gates opposing the body regions in the number of pillars and separated therefrom by a gate oxide;
• a number of control gates opposing the floating gates;
• a number of buried sourcelines disposed below the number of pillars and coupled to the first source/drain regions along a first selected direction in the array of memory cells;
• a number of control gate lines formed integrally with the number of control gates along a second selected direction in the array of flash memory cells, wherein the number of control gates are separated from the floating gates by a low tunnel barrier intergate insulator having a number of small compositional ranges such that gradients can be formed by an applied electric field which produce different barrier heights at an interface with the floating gate and control gate;
• and
• a number of bitlines coupled to the second source/drain regions along a third selected direction in the array of flash cells;
• wherein each floating gate is a horizontally oriented floating gate formed in a trench below a top surface of each pillar such that each trench houses a floating gate opposing the body regions in adjacent pillars on opposing sides of the trench, and wherein each horizontally oriented floating gate has a vertical length of less than 100 nanometers opposing the body region of the pillars.

An electronic system, comprising:

• a processor;
• and
• a memory device coupled to the processor, wherein the memory device and/or processor includes an array of p-channel depletion mode flash memory cells comprising:
• a number of pillars extending outwardly from a substrate, wherein each pillar includes a first source/drain region, a body region having a p-type depletion mode channel region, and a second source/drain region;
• a number of floating gates opposing the body regions in the number of pillars and separated therefrom by a gate oxide;
• a number of control gates opposing the floating gates;
• a number of buried sourcelines disposed below the number of pillars and coupled to the first source/drain regions along a first selected direction in the array of memory cells;
• a number of control gate lines formed integrally with the number of control gates along a second selected direction in the array of flash memory cells, wherein the number of control gates are separated from the floating gates by a low tunnel barrier intergate insulator having a number of small compositional ranges such that gradients can be formed by an applied electric field which produce different barrier heights at an interface with the floating gate and control gate;
• and
• a number of bitlines coupled to the second source/drain regions along a third selected direction in the array of flash cells.

An electronic system, comprising:

• a processor;
• and
• a memory device coupled to the processor, wherein at least one of the memory device and the processor includes an array of p-channel depletion mode flash memory cells comprising:
• a number of pillars extending outwardly from a substrate, wherein each pillar includes a first source/drain region, a body region having a p-type depletion mode channel region, and a second source/drain region;
• a number of floating gates opposing the body regions in the number of pillars and separated therefrom by a gate oxide;
• a number of control gates opposing the floating gates;
• a number of buried sourcelines disposed below the number of pillars and coupled to the first source/drain regions along a first selected direction in the array of memory cells;
• a number of control gate lines formed integrally with the number of control gates along a second selected direction in the array of flash memory cells, wherein the number of control gates are separated from the floating gates by a low tunnel barrier intergate insulator having a number of small compositional ranges such that gradients can be formed by an applied electric field which produce different barrier heights at an interface with the floating gate and control gate;
• and
• a number of bitlines coupled to the second source/drain regions along a third selected direction in the array of flash cells;
• wherein each control gate includes a polysilicon control gate having a metal layer formed thereon in contact with the low tunnel barrier intergate insulator, wherein the metal layer formed on the polysilicon control gate includes a metal layer that has a different work function than the metal layer formed on the floating gate;
• and
• wherein metal layer formed on the floating gate includes a parent metal for the asymmetrical low tunnel barrier intergate insulator and the metal layer formed on the control gate includes a metal layer having a work function in the range of 2.7 eV to 5.8 eV.

An electronic system, comprising:

• a processor;
• and
• a memory device coupled to the processor, wherein at least one of the memory device and the processor includes an array of p-channel depletion mode flash memory cells comprising:
• a number of pillars extending outwardly from a substrate, wherein each pillar includes a first source/drain region, a body region having a p-type depletion mode channel region, and a second source/drain region;
• a number of floating gates opposing the body regions in the number of pillars and separated therefrom by a gate oxide;
• a number of control gates opposing the floating gates;
• a number of buried sourcelines disposed below the number of pillars and coupled to the first source/drain regions along a first selected direction in the array of memory cells;
• a number of control gate lines formed integrally with the number of control gates along a second selected direction in the array of flash memory cells, wherein the number of control gates are separated from the floating gates by a low tunnel barrier intergate insulator having a number of small compositional ranges such that gradients can be formed by an applied electric field which produce different barrier heights at an interface with the floating gate and control gate;
• and
• a number of bitlines coupled to the second source/drain regions along a third selected direction in the array of flash cells;
• wherein each floating gate is a horizontally oriented floating gate formed in a trench below a top surface of each pillar such that each trench houses a floating gate opposing the body regions in adjacent pillars on opposing sides of the trench, and wherein each horizontally oriented floating gate has a vertical length of less than 100 nanometers opposing the body region of the pillars.