Memory circuitry

Memory circuitry comprising:

• a memory array comprising a plurality of memory cell capacitors, individual of the capacitors comprising a storage node electrode, a capacitor dielectric region, and a cell electrode;
• the cell electrode being commonly shared among at least some of the plurality of memory cell capacitors within the memory array;
• and
• the cell electrode within the memory array comprising a conductor metal layer comprising at least one of elemental tungsten, a tungsten alloy, tungsten silicide and tungsten nitride;
• the cell electrode comprising a conductive metal nitride different in composition from and in addition to the conductor metal layer;
• polysilicon being received over the conductor metal layer and over the conductive metal nitride;
• the conductor metal layer and the polysilicon being received over the storage node electrodes of said at least some of the plurality of memory cell capacitors;
• the polysilicon being received on the conductive metal nitride and on at least one of the elemental tungsten, tungsten alloy, tungsten silicide or tungsten nitride of the conductor metal layer.

Memory circuitry comprising:

• a memory array comprising a plurality of memory cell capacitors, individual of the capacitors comprising a storage node electrode, a capacitor dielectric region, and a cell electrode;
• the cell electrode being commonly shared among at least some of the plurality of memory cell capacitors within the memory array;
• and
• the cell electrode within the memory array comprising a conductor metal layer comprising at least one of elemental tungsten, a tungsten alloy, tungsten silicide and tungsten nitride;
• polysilicon being received over the conductor metal layer;
• the conductor metal layer and the polysilicon being received over the storage node electrodes of said at least some of the plurality of memory cell capacitors, the conductor metal layer being received over only a portion of each individual of said storage node electrodes of said at least some of the plurality of memory cell capacitors.

Memory circuitry comprising:

• a memory array comprising a plurality of memory cell capacitors, individual of the capacitors comprising a storage node electrode, a capacitor dielectric region, and a cell electrode;
• the cell electrode being commonly shared among at least some of the plurality of memory cell capacitors within the memory array;
• and
• the cell electrode within the memory array comprising a conductor metal layer comprising at least one of elemental tungsten, a tungsten alloy, tungsten silicide and tungsten nitride;
• polysilicon being received over the conductor metal layer;
• the conductor metal layer and the polysilicon being received over the storage node electrodes of said at least some of the plurality of memory cell capacitors, the storage node electrodes of said at least some of the plurality of memory cell capacitors comprising a container shape, the conductor metal layer being received over only a portion of each container shape of said storage node electrodes of said at least some of the plurality of memory cell capacitors.

Memory circuitry comprising:

• a memory array comprising a plurality of memory cell capacitors, individual of the capacitors comprising a storage node electrode, a capacitor dielectric region, and a cell electrode;
• the cell electrode being commonly shared among at least some of the plurality of memory cell capacitors within the memory array;
• the cell electrode within the memory array comprising:
• a conductive metal nitride layer;
• and
• a conductor metal layer comprising at least one of elemental tungsten, a tungsten alloy, tungsten silicide and tungsten nitride;
• the conductor metal layer being different in composition from the conductive metal nitride layer;
• and
• polysilicon received over both of the conductive metal nitride layer and the conductor metal layer;
• the conductive metal nitride layer, the conductor metal layer and the polysilicon being received over the storage node electrodes of said at least some of the plurality of memory cell capacitors, the polysilicon not comprising a conductive part of the cell electrode.

Memory circuitry comprising:

• a memory array comprising a plurality of memory cell capacitors, individual of the capacitors comprising a storage node electrode, a capacitor dielectric region, and a cell electrode;
• the cell electrode being commonly shared among at least some of the plurality of memory cell capacitors within the memory array;
• the cell electrode within the memory array comprising:
• a conductive metal nitride layer;
• and
• a conductor metal layer comprising at least one of elemental tungsten, a tungsten alloy, tungsten silicide and tungsten nitride;
• the conductor metal layer being different in composition from the conductive metal nitride layer;
• and
• polysilicon received over both of the conductive metal nitride layer and the conductor metal layer;
• the conductive metal nitride layer, the conductor metal layer and the polysilicon being received over the storage node electrodes of said at least some of the plurality of memory cell capacitors, the polysilicon being received on both of:
• a) the conductive metal nitride layer, and b) at least one of the elemental tungsten, tungsten alloy, tungsten silicide or tungsten nitride of the conductor metal layer.

Memory circuitry comprising:

• a memory array comprising a plurality of memory cell capacitors, individual of the capacitors comprising a storage node electrode, a capacitor dielectric region, and a cell electrode;
• the cell electrode being commonly shared among at least some of the plurality of memory cell capacitors within the memory array;
• the cell electrode within the memory array comprising:
• a conductive metal nitride layer;
• and
• a conductor metal layer comprising at least one of elemental tungsten, a tungsten alloy, tungsten silicide and tungsten nitride;
• the conductor metal layer being different in composition from the conductive metal nitride layer;
• and
• polysilicon received over both of the conductive metal nitride layer and the conductor metal layer;
• the conductive metal nitride layer, the conductor metal layer and the polysilicon being received over the storage node electrodes of said at least some of the plurality of memory cell capacitors, the conductor metal layer being received over only a portion of each individual of said storage node electrodes of said at least some of the plurality of memory cell capacitors.

Memory circuitry comprising:

• a memory array comprising a plurality of memory cell capacitors, individual of the capacitors comprising a storage node electrode, a capacitor dielectric region, and a cell electrode;
• the cell electrode being commonly shared among at least some of the plurality of memory cell capacitors within the memory array;
• the cell electrode within the memory array comprising:
• a conductive metal nitride layer;
• and
• a conductor metal layer comprising at least one of elemental tungsten, a tungsten alloy, tungsten silicide and tungsten nitride;
• the conductor metal layer being different in composition from the conductive metal nitride layer;
• and
• polysilicon received over both of the conductive metal nitride layer and the conductor metal layer;
• the conductive metal nitride layer, the conductor metal layer and the polysilicon being received over the storage node electrodes of said at least some of the plurality of memory cell capacitors, the storage node electrodes of said at least some of the plurality of memory cell capacitors comprising a container shape, the conductor metal layer being received over only a portion of each container shape of said storage node electrodes of said at least some of the plurality of memory cell capacitors.

Memory circuitry comprising:

• a memory array comprising a plurality of memory cell capacitors, individual of the capacitors comprising a storage node electrode, a capacitor dielectric region, and a cell electrode;
• the cell electrode being commonly shared among at least some of the plurality of memory cell capacitors within the memory array;
• the storage node electrodes being of a container shape and received within container openings formed within an insulative silicate glass;
• the cell electrode within the memory array comprising:
• a conductive metal nitride layer having a container shape;
• a conductor metal layer received on the conductive metal nitride layer, the conductive metal layer comprising at least one of elemental tungsten, a tungsten alloy, tungsten silicide and tungsten nitride in contact with the conductive metal nitride layer;
• the conductor metal layer being different in composition from the conductive metal nitride layer;
• and
• polysilicon received on both of a) the at least one of the elemental tungsten, tungsten alloy, tungsten silicide or tungsten nitride of the conductor metal layer and, b) the conductive metal nitride layer;
• the conductive metal nitride layer, the conductor metal layer and the polysilicon being received over the storage node electrodes of said at least some of the plurality of memory cell capacitors;
• the polysilicon filling last-remaining volume of said container shapes of the storage node electrodes.

Memory circuitry comprising:

• a memory array comprising a plurality of memory cell capacitors, individual of the capacitors comprising a storage node electrode, a capacitor dielectric region, and a cell electrode;
• the cell electrode being commonly shared among at least some of the plurality of memory cell capacitors within the memory array;
• the storage node electrodes being of a container shape and received within container openings formed within an insulative silicate glass;
• the cell electrode within the memory array comprising:
• a conductive metal nitride layer having a container shape;
• a conductor metal layer received on the conductive metal nitride layer, the conductive metal layer comprising at least one of elemental tungsten, a tungsten alloy, tungsten silicide and tungsten nitride in contact with the conductive metal nitride layer;
• the conductor metal layer being different in composition from the conductive metal nitride layer;
• and
• polysilicon received on the at least one of the elemental tungsten, tungsten alloy, tungsten silicide or tungsten nitride of the conductor metal layer;
• the conductive metal nitride layer, the conductor metal layer and the polysilicon being received over the storage node electrodes of said at least some of the plurality of memory cell capacitors;
• the polysilicon filling last-remaining volume of said container shapes of the storage node electrodes, the polysilicon not comprising a conductive part of the cell electrode.

Memory circuitry comprising:

• a memory array comprising a plurality of memory cell capacitors, individual of the capacitors comprising a storage node electrode, a capacitor dielectric region, and a cell electrode;
• the cell electrode being commonly shared among at least some of the plurality of memory cell capacitors within the memory array;
• the storage node electrodes being of a container shape and received within container openings formed within an insulative silicate glass;
• the cell electrode within the memory array comprising:
• a conductive metal nitride layer having a container shape;
• a conductor metal layer received on the conductive metal nitride layer, the conductive metal aver comprising at least one of elemental tungsten, a tungsten alloy, tungsten silicide and tungsten nitride in contact with the conductive metal nitride layer;
• the conductor metal layer being different in composition from the conductive metal nitride layer;
• and
• polysilicon received on the at least one of the elemental tungsten, tungsten alloy, tungsten silicide or tungsten nitride of the conductor metal layer;
• the conductive metal nitride layer, the conductor metal layer and the polysilicon being received over the storage node electrodes of said at least some of the plurality of memory cell capacitors;
• the polysilicon filling last-remaining volume of said container shapes of the storage node electrodes, the conductor metal layer being received over only a portion of each individual of said storage node electrodes of said at least some of the plurality of memory cell capacitors.

Memory circuitry comprising:

• a memory array comprising a plurality of memory cell capacitors, individual of the capacitors comprising a storage node electrode, a capacitor dielectric region, and a cell electrode;
• the cell electrode being commonly shared among at least some of the plurality of memory cell capacitors within the memory array;
• the storage node electrodes being of a container shape and received within container openings formed within an insulative silicate glass;
• the cell electrode within the memory array comprising:
• a conductive metal nitride layer having a container shape;
• a conductor metal layer received on the conductive metal nitride layer, the conductive metal layer comprising at least one of elemental tungsten, a tungsten alloy, tungsten silicide and tungsten nitride in contact with the conductive metal nitride layer;
• the conductor metal layer being different in composition from the conductive metal nitride layer;
• and
• polysilicon received on the at least one of the elemental tungsten, tungsten alloy, tungsten silicide or tungsten nitride of the conductor metal layer;
• the conductive metal nitride layer, the conductor metal layer and the polysilicon being received over the storage node electrodes of said at least some of the plurality of memory cell capacitors;
• the polysilicon filling last-remaining volume of said container shapes of the storage node electrodes;
• the polysilicon being substantially laterally coextensive with the conductive metal nitride layer at least within the memory array;
• and
• the conductor metal layer being received over only a portion of each individual of said storage node electrodes of said at least some of the plurality of memory cell capacitors.