Back to results
US 7,126,173 B2Granted
Method for enhancing the electric connection between a power electronic device and its package
AssigneeSTMicroelectronics S.r.l.
InventorsFerruccio Frisina, Antonio Pinto, Angelo Magri
Life of this patent
Estimating the term…
Abstract
An electronic power device of improved structure is fabricated with MOS technology to have a gate finger region and corresponding source regions on either sides of the gate region. This device has a first-level metal layer arranged to independently contact the gate region and source regions, and has a protective passivation layer arranged to cover the gate region. Advantageously, a wettable metal layer, deposited onto the passivation layer and the first-level metal layer, overlies said source regions. In this way, the additional wettable metal layer is made to act as a second-level metal.
Claims33
An electronic power device fabricated with MOS technology, the power device comprising:
- a gate finger region;
- associated first and second source regions positioned at opposite sides of the gate finger region;
- a first-level metal layer having a first metal portion contacting said gate finger region, a second metal portion contacting said first source region, and a third metal portion contacting said second source region;
- a dielectric passivation layer arranged to cover the gate finger region;
- and
- a wettable metal layer formed directly on a portion of the passivation layer directly above the gate finger region and the second and third metal portions of the first-level metal layer, wherein the wettable metal layer contacts and extends continuously between the second and third metal portions of the first-level metal layer.
3 more elements
An electronic power device, comprising:
- a gate region;
- associated source regions positioned at opposite sides of the gate region;
- a protective passivation layer arranged to cover the gate region;
- an adhesive layer positioned above the passivation layer;
- prevention means for preventing chemical reaction of the adhesive layer and the passivation layer;
- a thin bridge layer covering the adhesive layer, wherein the thin bridge layer is shaped to have supporting feet-shaped side projections positioned laterally of a central portion of the adhesive layer.
3 more elements
An electronic power device, comprising:
- a gate region;
- associated source regions positioned at opposite sides of the gate region;
- a protective passivation layer arranged to cover the gate region;
- an adhesive layer positioned above the passivation layer;
- prevention means for preventing chemical reaction of the adhesive layer and the passivation layer;
- and
- a thin bridge layer covering the adhesive layer, wherein the gate region is one of a plurality of gate regions occupying a whole area and the thin bridge layer is extended to overlap the whole area occupied by the plurality of gate regions, and has peripheral supporting projections positioned laterally of a central portion of the adhesive layer.
4 more elements
An electronic power device, comprising:
- a gate finger region;
- corresponding source regions on opposite sides of the gate finger region;
- a first-level metal layer formed over, and independently contacting, the gate finger region and the source regions;
- and
- a dielectric passivation layer covering the gate finger region and partly overlapping the first-level metal layer;
- and
- a wettable metal layer positioned directly on top of the passivation layer and directly above the gate finger region and the source regions, wherein the wettable metal layer contacts and extends continuously between portions of the first-level metal layer that contact the source regions.
4 more elements
An electronic power device fabricated with MOS technology, the power device comprising:
- a gate finger region;
- associated source regions positioned at opposite sides of the gate finger region;
- a first-level metal layer arranged to independently contact said gate finger region and said source regions;
- a protective passivation layer arranged to cover the gate finger region;
- and
- a wettable metal layer deposited onto the passivation layer and the first-level metal layer overlying said source regions, wherein said wettable metal layer is a triple layer comprising a stack structure of titanium, nickel and gold, wherein said wettable metal layer is coated with a solder layer covered by a thin bridge layer, wherein said thin bridge layer is shaped to have supporting feet-shaped side projections arranged to reach down to portions of said first-level metal layer overlying said source regions.
3 more elements
An electronic power device fabricated with MOS technology, the power device comprising:
- a gate finger region;
- associated source regions positioned at opposite sides of the gate finger region;
- a first-level metal layer arranged to independently contact said gate finger region and said source regions;
- a protective passivation layer arranged to cover the gate finger region;
- and
- a wettable metal layer deposited onto the passivation layer and the first-level metal layer overlying said source regions, wherein said wettable metal layer is a triple layer comprising a stack structure of titanium, nickel and gold, wherein said wettable metal layer is coated with a solder layer covered by a thin bridge layer, wherein the gate finger region is one of a plurality of gate finger regions occupying a whole area and said thin bridge layer is extended to overlap the whole area occupied by the plurality of gate finger regions, and has peripheral supporting projections arranged to reach down to portions of said first-level metal layer overlying said source regions on opposite sides of the gate finger regions.
3 more elements
An electronic power device fabricated with MOS technology, the power device comprising:
- a gate finger region;
- associated first and second source regions positioned at opposite sides of the gate finger region;
- a first-level metal layer having a first metal portion contacting said gate finger region, a second metal portion contacting said first source region, and a third metal portion contacting said second source region;
- a dielectric passivation layer arranged to cover the gate finger region;
- and
- a wettable metal layer formed directly on a portion of the passivation layer directly above the gate finger region and the second and third metal portions of the first-level metal layer, wherein said wettable metal layer is coated with a solder layer covered by a thin bridge layer, wherein said thin bridge layer is shaped to have supporting feet-shaped side projections arranged to reach down to said source regions.
3 more elements
An electronic power device fabricated with MOS technology, the power device comprising:
- a gate finger region;
- associated first and second source regions positioned at opposite sides of the gate finger region;
- a first-level metal layer having a first metal portion contacting said gate finger region, a second metal portion contacting said first source region, and a third metal portion contacting said second source region;
- a dielectric passivation layer arranged to cover the gate finger region;
- and
- a wettable metal layer formed directly on a portion of the passivation layer directly above the gate finger region and the second and third metal portions of the first-level metal layer, wherein said wettable metal layer is coated with a solder layer covered by a thin bridge layer, wherein the gate finger region is one of a plurality of gate finger regions occupying a whole area and said thin bridge layer is extended to overlap the whole area occupied by the plurality of gate finger regions, and has peripheral supporting projections arranged to reach down to said source regions on opposite sides of the gate finger regions.
3 more elements
An electronic power device, comprising:
- a gate finger region;
- corresponding source regions on opposite sides of the gate finger region;
- a first-level metal layer formed over, and independently contacting, the gate finger region and the source regions;
- and
- a dielectric passivation layer covering the gate finger region and partly overlapping the first-level metal layer;
- a wettable metal layer positioned directly on top of the passivation layer and directly above the gate finger region and the source regions;
- a solder layer covering the wettable metal layer and formed with two reduced regions on opposite sides of the gate finger region;
- and
- a thin bridge layer on the solder layer such that supporting feet-shaped side projections from said bridge layer fit in said reduced regions.
6 more elements
An electronic power device, comprising:
- a gate finger region;
- corresponding source regions on opposite sides of the gate finger region;
- a first-level metal layer formed over, and independently contacting, the gate finger region and the source regions;
- and
- a dielectric passivation layer covering the gate finger region and partly overlapping the first-level metal layer;
- a wettable metal layer positioned directly on top of the passivation layer and directly above the gate finger region and the source regions;
- a solder layer covering the wettable metal layer;
- and
- a thin bridge layer on the solder layer, wherein the gate finger region is one of a plurality of gate finger regions occupying a whole area and said thin bridge layer is extended to overlap the whole area occupied by the plurality of gate finger regions, and has peripheral supporting projections arranged to reach down to said source regions on opposite sides of the gate finger regions.
6 more elements
Dependencies are inferred from the claim text.