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US 7,126,164 B2Granted
Wafer-level moat structures
AssigneeFlipChip International, LLC
InventorsMichael E. Johnson, Peter Elenius, Deok Hoon Kim
Life of this patent
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AssigneeFlipChip International, LLC
InventorsMichael E. Johnson, Peter Elenius, Deok Hoon Kim
Estimating the term…
A wafer-level CSP (200) includes at least one die (202) from a wafer. The wafer-level CSP has a plurality of solder ball pads (206), a solder ball (308) at each solder ball pad and a polymer collar (310) around each solder ball. A moat (204) is formed in the surface of a polymer layer (412) disposed on the wafer during manufacturing of the wafer-level CSP. A temporarily liquified residual (502) from the polymer collar, which occurs while the wafer is heated to the reflow temperature of the solder ball, flows from the polymer collar. The moat acts as a barrier to material flow, limiting the distance that the residual spreads while liquified. The residual from the polymer collar remains within a region (314) defined by the moat. A full-depth moat (312) extends completely through the polymer layer. Alternatively, a partial-depth moat (712 and 912) extends partially through the polymer layer. The abstract is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims pursuant to 37 C.F.R. §1.72(b).
A chip scale package of an integrated circuit, comprising:
A wafer for a chip scale package, the wafer having at least one solder ball pad, comprising:
A chip scale package of an integrated circuit, comprising:
A chip scale package of an integrated circuit, comprising:
A chip scale package of an integrated circuit disposed in a semiconductor substrate, comprising:
Dependencies are inferred from the claim text.