S-parameter power plane probe coupon
AssigneeEMC Corporation
InventorsBashu Kanal, Michael Creighton
Life of this patent
Estimating the term…
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AssigneeEMC Corporation
InventorsBashu Kanal, Michael Creighton
Estimating the term…
A test point on a printed circuit board includes at least one connection to the power plane having first and second interconnected pads disposed on opposing sides of the power plane, and at least one connection to the ground plane having third and fourth interconnected pads disposed on opposing sides of the ground plane. The first and second interconnected pads provide parallel paths to the power plane, thereby reducing the impedance presented to test equipment. Similarly, The third and fourth interconnected pads provide parallel paths to the ground plane. The test point may be implemented with multiple ground plane connections disposed symmetrically around a power plane connection. For example, first and second ground plane connections may be disposed on opposing sides of a power plane connection to provide shielding to the power plane connection, thereby reducing the inductive loop associated with probe parasitics.
A test point for a printed circuit board having first and second outer layers, and a power layer and a ground layer disposed between the first and second outer layers, comprising:
A method of providing a test point for a printed circuit board having first and second outer layers, and a power layer and a ground layer disposed between the first and second outer layers, comprising the steps of:
Dependencies are inferred from the claim text.