Test structure for a single-sided buried strap DRAM memory cell array

A test structure for determining the electrical properties of memory cells, comprising:

• a selection transistor and a storage capacitor, in a matrix-like cell array, where the selection transistors have an active region with a gate electrode, where the active region is conductively connected to a bit line and an internal electrode in the storage capacitor, and the gate electrode is conductively connected to a word line, where the active regions of the selection transistors are arranged in rows in a first direction, and the storage capacitors are arranged in rows in a second direction, which runs transversely with respect to the first direction, where the conductive connection between the active region of the selection transistor and the internal electrode in the storage capacitor in the memory cells on overlapping areas of the crossing rows of active regions and storage capacitors is respectively produced in a single edge region of the overlapping area, where the bit lines run in the first direction, making contact with the active regions of the selection transistors in the first direction, and the word lines run in the second direction, making contact with the gate electrodes of the selection transistors in the second direction, wherein
• the internal electrodes in the storage capacitors in two adjacent memory cells are connected to one another to produce a series circuit comprising the first selection transistor, the first storage capacitor, the second storage capacitor and the second selection transistor in the two adjacent memory cells, the active regions of the first and second selection transistors not being connected by means of the bit line which makes contact with the first and second selection transistors.