US 7,125,780 B2 · Dielectric isolation type semiconductor device and method for manufacturing the same

Abstract

A dielectric isolation type semiconductor device and a manufacturing method therefor achieve high dielectric resistance while preventing the dielectric strength of the semiconductor device from being limited depending on the thickness of a dielectric layer and the thickness of a first semiconductor layer. A semiconductor substrate (1) and an n− type semiconductor layer (2) are bonded to each other through a buried oxide film layer (3). A first porous oxide film area (10) is formed in the semiconductor substrate in a state contacting with the buried oxide film layer. A power device is formed on the n− type semiconductor layer. The first porous oxide film area is formed in an area including a location right under a first main electrode (6) and extending from the first main electrode side up to a range of more than 40% of a distance (L) between the first and second main electrodes (6, 7).

Claims6

Dependent claims

A method for manufacturing a dielectric isolation type semiconductor device in which a semiconductor substrate and an active layer are bonded to each other through a main dielectric layer, and a supplementary dielectric layer comprising a porous oxide film is formed in said semiconductor substrate in a state contacting with said main dielectric layer, with a power device being formed on said active layer, said method comprising:

a step of forming a p+ diffusion area and an n+ diffusion area on a principal plane of said semiconductor substrate;
a step of forming an n+ buried diffusion area at a location under said p+ diffusion area in such a manner that said buried n+ diffusion area is in contact with said p+ diffusion area and overlaps with a lower portion of an outer periphery of said n+ diffusion area in a manner apart therefrom;
a step of making said p+ diffusion area porous to a depth up to said n+ buried diffusion area;
a step of oxidizing the principal plane side of said semiconductor substrate and said area that has been made porous;
a step of bonding said semiconductor substrate and an active layer side silicon substrate to each other;
a step of polishing said active layer side silicon substrate to form said active layer;
and
a step of forming said power device on said active layer.

5 more elements

a step of forming a p+ diffusion area and an n+ diffusion area on a principal plane of said semiconductor substrate;
a step of making said p+ diffusion area porous to form a porous area;
a step of removing a part of that portion of an oxide film layer formed on a rear surface of an active layer side silicon substrate which corresponds to a location right under said isolation area;
a step of bonding said semiconductor substrate and an active layer side silicon substrate to each other;
a step of polishing said active layer side silicon substrate to form said active layer;
a step of forming said isolation area on said active layer;
a step of forming said power device in said isolation area on said active layer;
a step of forming, at a location of said isolation area, an opening portion extending from a front surface of said active layer to said porous area through a removal area in which the part of said oxide film layer is removed;
and
a step of exposing said porous area to a high ozone concentration atmosphere or a thermal oxidation atmosphere through said opening portion to oxidize said porous area thereby to form said supplementary dielectric layer.

7 more elements

Dependencies are inferred from the claim text.

Dielectric isolation type semiconductor device and method for manufacturing the same

Life of this patent

Dielectric isolation type semiconductor device and method for manufacturing the same

Life of this patent

Abstract

Claims6