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US 7,125,776 B2Granted
Multi-step chemical mechanical polishing of a gate area in a FinFET
AssigneeAdvanced Micro Devices, Inc.
InventorsKrishnashree Achuthan, Shibly S. Ahmed, Haihong Wang, Bin Yu
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Abstract
A method of manufacturing a MOSFET type semiconductor device includes planarizing a gate material layer that is deposited over a channel. The planarization is performed in a multi-step process that includes an initial “rough” planarization and then a “fine” planarization. The slurry used for the finer planarization may include added material that tends to adhere to low areas of the gate material.
Claims20
A method of manufacturing a semiconductor device, comprising:
- forming a fin structure on an insulator;
- forming a gate structure over at least a portion of the fin structure and a portion of the insulator;
- planarizing the gate structure by performing a chemical mechanical polishing (CMP) of the gate structure using a first slurry;
- and
- planarizing the gate structure in a second planarization by performing a CMP of the gate structure using a second slurry different than the first slurry, the second planarization of the gate structure raising a height of the gate structure surrounding the fin structure.
2 more elements
A method for forming a MOSFET device comprising:
- forming a source, a drain, and a fin structure on an insulating layer, portions of the fin structure acting as a channel for the MOSFET;
- forming a dielectric layer around the fin structure;
- depositing a polysilicon layer over the fin structure, the polysilicon layer acting as a gate area for the MOSFET;
- planarizing the polysilicon layer at a first rate;
- and
- further planarizing the polysilicon layer at a second rate slower than the first rate, and wherein the further planarization of the polysilicon layer raises a height of the polysilicon layer in areas adjacent the fin structure.
3 more elements
A method for forming a MOSFET device comprising:
- forming a source region on an insulating layer;
- forming a drain region on the insulating layer;
- forming a fin structure on the insulating layer, portions of the fin structure acting as a channel for the MOSFET;
- depositing a polysilicon layer over at least portions of the fin structure and the insulating layer, the polysilicon layer acting as a gate area for the MOSFET and extending over the fin structure;
- performing a first planarization of the polysilicon layer at a first rate;
- and
- performing a second planarization of the polysilicon layer at a second rate slower than the first rate, the second planarization of the polysilicon layer raising a height of the polysilicon layer adjacent the fin structure;
- and
- doping the source and drain regions.
6 more elements
Dependencies are inferred from the claim text.