Method of manufacturing transistor having recessed channel
AssigneeSamsung Electronics Co., Ltd.
InventorsMin Kim, Ju-Bum Lee, Hyeon-Deok Lee, Seung-Jae Lee
Life of this patent
Estimating the term…
Abstract
A method of fabricating a transistor with a recessed channel is provided. The method includes forming trenches for a recessed channel on a semiconductor substrate, depositing an isolation layer on the semiconductor substrate on which the trenches are formed, depositing a gate dielectric layer on the semiconductor substrate so that the gate dielectric layer can be extended to bottoms and sidewalls of the trenches, forming gates to fill the trenches, and forming source and drain regions in the semiconductor substrate adjacent to the gates.
Claims18
A method of fabricating a transistor, comprising:
- forming trenches for a recessed channel in a semiconductor substrate;
- depositing a gate dielectric layer in the semiconductor substrate so that the gate dielectric layer extends to bottoms and sidewalls of the trenches;
- forming a first conductive layer to fill the trenches;
- thereafter, depositing an isolation layer in the semiconductor substrate in which the trenches are formed;
- forming a second conductive layer on the first conductive layer after the deposition of the isolation layer;
- patterning the first and second conductive layers during a same etching process to form gates that fill the trenches;
- and
- forming source and drain regions in the semiconductor substrate adjacent to the gates.
A method of fabricating a transistor, comprising:
- forming first trenches for a recessed channel in a semiconductor substrate;
- depositing a gate dielectric layer on the semiconductor substrate in which the first trenches are formed;
- forming a first conductive layer on the gate dielectric layer to fill the first trenches;
- forming second trenches in the semiconductor substrate;
- depositing an isolation layer to fill the second trenches;
- forming a second conductive layer to cover upper portions of the first conductive layer and the isolation layer, wherein forming the second conductive layer includes
- forming a polycrystalline silicon layer on the first conductive layer so that the polycrystalline silicon layer extends to the isolation layer, and
- forming a metal layer or a metal suicide layer on the polycrystalline silicon layer;
- forming gates filling the first trenches by patterning the first and second conductive layers;
- and
- forming source and drain regions in the semiconductor substrate adjacent to the gates.
Dependencies are inferred from the claim text.