Process for manufacturing leadless semiconductor packages including an electrical test in a matrix of a leadless leadframe

A process for manufacturing a plurality of leadless semiconductor packages, comprising:

• providing a leadless leadframe having a packaging matrix, the packaging matrix defining a plurality of units and a plurality of cutting streets, a plated metal layer being formed on the units and the cutting streets;
• disposing a plurality of chips in the units;
• electrically connecting the chips with the plated metal layer;
• forming an encapsulant on the packaging matrix to cover the chips, the units and the cutting streets;
• etching the leadless leadframe;
• performing a first sawing step to cut out the plated metal layer along the cutting streets;
• electrically testing the encapsulated chips through the plated metal layer by probing after the first sawing step;
• and
• performing a second sawing step after the electrically testing step, the encapsulant being cut along the cutting streets to form a plurality of individual package bodies of the leadless semiconductor packages.

A process for manufacturing a plurality of leadless semiconductor packages, comprising:

• providing a leadless leadframe having a packaging matrix, the packaging matrix having a plurality of units and a plurality of connecting bars, wherein each unit has a plurality of leads connected to the connecting bars, a plated metal layer is formed on the upper surfaces of the leads and the upper surfaces of the connecting bars;
• bonding a plurality of chips to the units and electrically connecting the chips to the plated metal layer on the leads;
• forming an encapsulant on the packaging matrix of the leadless leadframe to cover the plated metal layer on the upper surfaces of the leads and the connecting bars;
• etching the connecting bars to form a plurality of grooves exposing portions of the plated metal layer;
• performing a first sawing step to cut out the exposed plated metal layer in the grooves;
• electrically testing the encapsulated chips after the first sawing step;
• and
• performing a second sawing step after the electrical testing, the encapsulant being cut along the grooves to form a plurality of individual package bodies of the leadless semiconductor packages.