US 7,124,221 B1 · Low latency multi-level communication interface

Abstract

A memory system uses multiple pulse amplitude modulation (multi-PAM) output drivers and receivers to send and receive multi-PAM sigsnals. A multi-PAM signal has more than two voltage levels, with each data interval now transmitting a “symbol” at one of the valid voltage levels. In one embodiment, a symbol represents two or more bits. The multi-PAM output driver drives an output symbol onto a signal line. The output symbol represents at least two bits that include a most significant bit (MSB) and a least significant bit (LSB). The multi-PAM receiver receives the output symbol from the signal line and determines the MSB and the LSB.

Claims37

Dependent claims

A multi-mode pulse-amplitude-modulation (PAM) receiver for receiving a sequence of symbols, the receiver comprising:

a receiver circuit configured to receive the sequence of symbols;
and
logic circuitry coupled to the receiver circuit;
wherein the multi-mode PAM receiver is capable of operating in a specified mode of a plurality of predefined modes;
wherein the received symbols are N-PAM symbols when the specified mode is a first mode, each respective N-PAM symbol in the sequence of received symbols having one of N distinct symbol values;
wherein the received symbols are M-PAM symbols when the specified mode is a second mode, each respective M-PAM symbol in the sequence of received symbols having one of M distinct symbol values;
and
wherein N is not equal to M.

5 more elements

Dependencies are inferred from the claim text.

Low latency multi-level communication interface

Life of this patent

Low latency multi-level communication interface

Life of this patent

Abstract

Claims37