US 7,120,915 B1 · Thread switch circuit design and signal encoding for vertical threading

Abstract

A method and apparatus for implementing vertical multi-threading in a microprocessor without implementing additional signal wires in the processor has been developed. The method uses a pre-existing signal to serve as a multi-function signal such that the multi-function signal can be used for clock enable, clock disable, and scan enable functions. The single multi-function signal exhibits multiple functionalities as needed by a flip-flop to operate in a plurality of modes. The method allows for the use of a pre-existing signal wire to be used as a process thread switch signal that would otherwise have to be explicitly hard-wired in the absence of the multi-functioning signal. The method further includes allowing multiple-bit flip-flops to be placed at sequential stages in a pipeline in order to facilitate vertical multi-threading and, in effect, increase processor performance. The apparatus provides means for distinguishing between specific characteristics exhibited by the multi-function signal. The apparatus further provides means for generating intermediary signals within a control block and then generating output signals to a data storage block. The apparatus also involves generating timing signals to a plurality of flip-flops dependent upon the behavior of the multi-function signal.

Claims38

Dependent claims

A system for implementing vertical threading in a processor, comprising:

a header block that receives a multi-function signal and generates a plurality of signals using the multi-function signal;
and
a data storage block that is responsive to the plurality of signals generated by the header block,
wherein the multi-function signal comprises a scan enable function, a clock enable function, and a clock disable function, and
wherein the determination that the multi-function signal serves as the scan enable function indicates that the multiple-bit flip-flop should operate in a scan mode, and wherein the determination that the multi-function signal serves as the clock enable function indicates that the multiple-bit flip-flop should operate in a normal mode.

2 more elements

An apparatus for implementing a vertical threading scheme, comprising:

means for inputting a clock signal;
means for inputting a multi-function signal;
means for inputting a global thread identifier signal;
means for distinguishing between different functionalities of the multi-function signal to determine which of a plurality of functions the multi-function serves, wherein the plurality of functions comprises a scan enable function a clock enable function, and a clock disable function;
and
means for generating a plurality of signals based on the determination of which of the plurality of functions the multi-function serves, the clock signal, and the global thread identifier signal,
wherein the determination that the multi-function signal serves as the scan enable function indicates that the multiple-bit flip-flop should operate in a scan mode, and wherein the determination that the multi-function signal serves as the clock enable function indicates that the multiple-bit flip-flop should operate in a normal mode.

4 more elements

Dependencies are inferred from the claim text.

Thread switch circuit design and signal encoding for vertical threading

Life of this patent

Thread switch circuit design and signal encoding for vertical threading

Life of this patent

Abstract

Claims38