Master slice semiconductor integrated circuit
AssigneeNEC Electronics Corporation
InventorKenji Yamamoto
Life of this patent
Estimating the term…
Abstract
It is an object of the present invention to reduce power consumption and improve flexibility in a master slice semiconductor integrated circuit. The master slice semiconductor integrated circuit comprises at least two wiring layers to form wirings, and a plurality of clock buffers connected by clock wirings in the form of a clock tree having at least two cascaded stages to distribute clock signals to a plurality of sequential circuits, wherein the clock wirings comprises a wiring layer switching portion which switches a wiring layer from a lower wiring layer of the at least two wiring layers to an upper wiring layer of the at least two wiring layers and then switches from the upper wiring layer to the lower wiring layer.
Claims14
A master slice semiconductor integrated circuit, comprising:
- at least two wiring layers for wiring;
- and
- a plurality of clock buffers connected by clock wirings in a form of a clock tree having at least two cascaded stages to distribute clock signals to a plurality of sequential circuits;
- wherein each of said clock wirings among said plurality of clock buffers comprises a wiring layer switching portion which switches a clock wiring from a lower wiring layer of said at least two wiring layers to an upper wiring layer of said at least two wiring layers and then switches said clock wiring from said upper wiring layer to said lower wiring layer;
- wherein said wiring layer switching portion comprises:
- an output wiring which is formed of said lower wiring layer and connects one end thereof to a clock output of a clock buffer of a former stage;
- an output side via wiring which connects one end thereof to the other end of said output wiring and connects the other end thereof to said upper wiring layer;
- an input wiring which is formed of said lower wiring layer and connects one end thereof to a clock input of a clock buffer of a later stage;
- and
- an input side via wiring which connects one end thereof to the other end of said input wiring and connects the other end thereof to said upper wiring layer;
- and
- wherein said upper wiring layer is a wiring layer for customized wirings, and said lower wiring layer is a wiring layer for fixed wirings.
A semiconductor device comprising:
- a semiconductor substrate;
- a first wiring layer above said semiconductor substrate, said first wiring layer being formed as a customized wiring layer such that a pattern of said first wiring layer is determined based on customer specifications;
- a second wiring layer between said semiconductor substrate and said first wiring layer, said second wiring layer being formed as a fixed wiring layer such that a pattern of said second wiring layer is determined independently of the customer specifications;
- a first clock output circuit formed in said semiconductor substrate and outputting a first clock signal through a first clock output wiring, said first clock output wiring being formed of said second wiring layer;
- a first clock input circuit formed in said semiconductor substrate and receiving the first clock signal through a first clock input wiring, said first clock input wiring being formed of said second wiring layer;
- and
- a first connecting wiring formed of said first wiring layer to make an electrical connection path between said first clock output wiring and said first clock input wiring.
A semiconductor device having a multilevel wiring structure including a lower-level wiring layer, an upper-level wiring layer and an insulating film intervening between said lower-level and upper-level wiring layers, said device comprising:
- a first wiring formed of said lower-level wiring layer to convey a first clock signal;
- a first via formed in said insulating film in contact with a part of said first wiring;
- a second wiring formed of said lower-level wiring layer to convey a second clock signal;
- a second via formed in said insulating film in contact with a part of said second wiring;
- a third wiring formed of said lower-level wiring layer;
- a third via formed in said insulating film in contact with a part of said third wiring;
- a fourth wiring formed of said lower-level wiring layer;
- a fourth via formed in said insulating film in contact with a part of said fourth wiring;
- a fifth wiring formed of said upper-level wiring layer in contact with said first via and said third via to thereby allow said first clock signal to be transferred to said third wiring;
- and
- Wherein:
- said fourth via being supplied with one of a power potential and a third clock signal and being free from connection with said second via;
- and
- said upper-level wiring layer is formed as a customized wiring layer such that a pattern of said upper-layer wiring layer is determined based on customer specifications, and said lower-level wiring layer being formed as a fixed wiring layer such that a pattern of said lower-layer wiring is determined independently of the customer specifications.
Dependencies are inferred from the claim text.