Apparatus for delay fault testing of integrated circuits

An apparatus for analyzing a failure in a semiconductor integrated circuit, comprising:

• a cell-list generation section generating a list of cells composing a path in the semiconductor integrated circuit with a delay fault based on a test result of whether the delay fault is generated on the path;
• a retrieval-condition designation section designating a retrieval condition configured to retrieve a fault-cell searching path, which includes a part of the path with the delay fault;
• a path-list generation section for fault-cell searching, which retrieves the fault-cell searching path based on the retrieval condition, and generates a fault-cell searching path list in which cells composing the retrieved fault-cell searching path are ordered according to the transmission of a signal by the cells composing the retrieved fault-cell searching path;
• a test-vector generation section for fault-cell searching, which generates a test vector based on the fault-cell searching path list;
• an ending-condition designation section designating an ending condition configured to end generation of the test vector;
• and
• an ending-condition judgment section stopping generation of the path list when the ending condition is satisfied.

A computer-implemented method for generating a test vector of a semiconductor integrated circuit comprising:

• designating a retrieval condition configured to select a path on which a signal can be transmitted in the semiconductor integrated circuit;
• executing a timing analysis of the semiconductor integrated circuit based on circuit information of the semiconductor integrated circuit, retrieving the path satisfying the retrieval condition, and generating a path list in which cells composing the retrieved path are ordered according to the timing analysis;
• generating a test vector configured to test a path delay fault of the semiconductor integrated circuit based on the path list;
• designating an ending condition configured to end generation of the test vector when the path in the path list for the test vector covers the semiconductor integrated circuit;
• and
• stopping generation of the path list when the ending condition is satisfied.

A computer program product to be executed by a computer for generating a test vector of a semiconductor integrated circuit comprising:

• instructions designating a retrieval condition configured to select a path on which a signal can be transmitted in the semiconductor integrated circuit;
• instructions executing a timing analysis of the semiconductor integrated circuit based on circuit information of the semiconductor integrated circuit, retrieving the path satisfying the retrieval condition, and generating a path list in which cells composing the retrieved path are ordered according to the timing analysis;
• instructions generating a test vector configured to test a path delay fault of the semiconductor integrated circuit based on the path list;
• instructions designating an ending condition configured to end generation of the test vector when the path in the path list for the test vector covers the semiconductor integrated circuit;
• and
• instructions stopping generation of the path list when the ending condition is satisfied.