LDPC code and encoder/decoder regarding same
AssigneeLeanics Corporation
InventorsTong Zhang, Keshab K. Parhi
Life of this patent
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Abstract
A joint code-encoder-decoder design approach and circuit architecture design for (3,k)-regular LDPC coding system implementation. The joint design process relies on a high girth (2,k)-regular LDPC code construction. The decoder realizes partly parallel decoding. The encoding scheme only contains multiplications between sparse matrices and vector and multiplication between a very small dense matrix and vector.
Claims19
An integrated circuit that implements a (2,k)-regular low-density parity check code decoder with the functionality of 2Lk check node functions and Lk2 variable node functions, comprising:
- (a) k2 random access memories (RAMs),
- (b) k2 variable node units, wherein one variable node unit is coupled to one RAM,
- (c) a bidirectional shuffle network connected to the said k2 RAMs,
- (d) k check node units connected to the said shuffle network, and
- (e) k2 modulo-L counters, wherein each modulo-L counter is an address generator for one RAM.
An integrated circuit that implements a (3,k)-regular low-density parity check code decoder with the functionality of 3Lk check node functions and Lk2 variable node functions, comprising:
- (a) k2 random access memories (RAMs),
- (b) k2 variable node units, wherein one variable node unit is coupled to one RAM,
- (c) a first bidirectional shuffle network that is connected to the said RAMs,
- (d) a second bidirectional shuffle network coupled to the first bidirectional shuffle network, wherein the permutations performed by the second shuffle network are controlled by a g-bit word,
- (e) a random pattern generator which is coupled to the said second shuffle network wherein the random pattern generator generates the g-bit word to control the permutations in the second shuffle network,
- (f) k check node units connected to the said second shuffle network, and
- (g) k2 modulo-L counters, wherein each modulo-L counter is an address generator for one RAM.
An integrated circuit that implements a (3,k)-regular low-density parity check code decoder with the functionality of 3Lk check node functions and Lk2 variable node functions, comprising:
- (a) k2 random access memories (RAMs),
- (b) k2 variable node units, wherein one variable node unit is coupled to one RAM,
- (c) a first bidirectional shuffle network that is connected to the said RAMs, wherein the permutations performed by the shuffle network are regular and fixed,
- (d) a second bidirectional shuffle network that is connected to the said RAMs, wherein the permutations performed by the said shuffle network are regular and fixed,
- (e) a third bidirectional shuffle network that is connected to the said RAMs, wherein the permutations performed by the said shuffle network are random-like and configurable,
- (f) k check node units connected to the first shuffle network,
- (g) k check node units connected to the second shuffle network,
- (h) k check node units connected to the third shuffle network,
- (i) k2 modulo-L counters, wherein each modulo-L counter is an address generator for one RAM.
Dependencies are inferred from the claim text.