System and method for performing scan test with single scan clock
AssigneeRealtek Semiconductor Corp.
InventorChi-Feng Wu
Life of this patent
Estimating the term…
Abstract
A logic system for performing scan test with single scan clock and related method. The logic system includes a first clock domain, which performs logic operations and scan tests with a first clock signal, and a second clock domain, which performs logic operations with a second clock signal and performs scan tests with the first clock signal.
Claims13
A logic system for performing scan tests with a single scan clock comprising:
- a first clock domain for performing logic operations and scan tests with a first clock signal, the first clock domain including at least one first-domain scan cell for buffering data;
- and
- a second clock domain for performing logic operations with a second clock signal and for performing scan tests with the first clock signal, the second clock domain including at least one second domain scan cell for buffering data.
A method for performing scan tests of a logic system, the logic system comprising a multiple clock domain scan test circuit having a first clock domain and a second clock domain, the first clock domain including at least one first-domain scan cell, the second clock domain including at least one second-domain scan cell, the method comprising:
- when the logic system performs logic operations, performing logic operations according to a first clock signal and a second clock signal in the first clock domain and the second clock domain respectively;
- and
- when the logic system performs scan tests, performing scan tests according to a test clock signal in both the first clock domain and the second clock domain so that the first clock domain and the second clock domain demonstrate clock tree balance characteristic or clock tree quasi-balance characteristic.
A method for performing scan tests in a logic system, the logic system comprising a first clock domain and a second clock domain, the method comprising:
- providing a mode signal, the value of which indicates a first mode or a second mode;
- operating the first clock domain referencing to a first clock signal during the first mode;
- operating the second clock domain referencing to a second clock signal being of a frequency different from a frequency of the first clock signal during the first mode;
- operating the first clock domain referencing to the first clock signal to perform a scan test in the first clock domain during the second mode;
- and
- operating the second clock domain referencing to the first clock signal to perform the scan test in the second clock domain during the second mode.
Dependencies are inferred from the claim text.